From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 32/47] memory: tegra-mc: Add interconnect framework Date: Wed, 4 Nov 2020 19:49:08 +0300 [thread overview] Message-ID: <20201104164923.21238-33-digetx@gmail.com> (raw) In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 22 ++++++++ include/soc/tegra/mc.h | 17 ++++++ 4 files changed, 140 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 9f0a96bf9ccc..b38e5255effe 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 998f9148ecb8..a7e6a8e4c95a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -639,6 +639,101 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_node *node; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!device_property_present(mc->dev, "#interconnect-cells") || + !mc->soc->icc_ops) + return 0; + + mc->provider.dev = mc->dev; + mc->provider.data = &mc->provider; + mc->provider.set = mc->soc->icc_ops->set; + mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < mc->soc->num_clients; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + } + + /* + * MC driver is registered too early, so early that generic driver + * syncing doesn't work for the MC. But it doesn't really matter + * since syncing works for the EMC drivers, hence we can sync the + * MC driver by ourselves and then EMC will complete syncing of + * the whole ICC state. + */ + icc_sync_state(mc->dev); + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -727,6 +822,11 @@ static int tegra_mc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + err = tegra_mc_interconnect_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); if (IS_ERR(mc->smmu)) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..33e40d600592 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -78,6 +78,20 @@ #define MC_TIMING_UPDATE BIT(0) +static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) +{ + val = val * percents; + do_div(val, 100); + + return min_t(u64, val, U32_MAX); +} + +static inline struct tegra_mc * +icc_provider_to_tegra_mc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_mc, provider); +} + static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -115,4 +129,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra ICC drivers. The ID numbers are + * chosen such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_MC 1000 +#define TEGRA_ICC_EMC 1001 +#define TEGRA_ICC_EMEM 1002 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d9395af98143..43876216de34 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -6,7 +6,9 @@ #ifndef __SOC_TEGRA_MC_H__ #define __SOC_TEGRA_MC_H__ +#include <linux/bits.h> #include <linux/err.h> +#include <linux/interconnect-provider.h> #include <linux/reset-controller.h> #include <linux/types.h> @@ -141,6 +143,17 @@ struct tegra_mc_reset_ops { const struct tegra_mc_reset *rst); }; +#define TEGRA_MC_ICC_TAG_DEFAULT 0 +#define TEGRA_MC_ICC_TAG_ISO BIT(0) + +struct tegra_mc_icc_ops { + int (*set)(struct icc_node *src, struct icc_node *dst); + int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, + void *data); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -160,6 +173,8 @@ struct tegra_mc_soc { const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; unsigned int num_resets; + + const struct tegra_mc_icc_ops *icc_ops; }; struct tegra_mc { @@ -178,6 +193,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Georgi Djakov <georgi.djakov@linaro.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Mikko Perttunen <cyndis@kapsi.fi>, Viresh Kumar <vireshk@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org> Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Subject: [PATCH v7 32/47] memory: tegra-mc: Add interconnect framework Date: Wed, 4 Nov 2020 19:49:08 +0300 [thread overview] Message-ID: <20201104164923.21238-33-digetx@gmail.com> (raw) In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 22 ++++++++ include/soc/tegra/mc.h | 17 ++++++ 4 files changed, 140 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 9f0a96bf9ccc..b38e5255effe 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 998f9148ecb8..a7e6a8e4c95a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -639,6 +639,101 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_node *node; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!device_property_present(mc->dev, "#interconnect-cells") || + !mc->soc->icc_ops) + return 0; + + mc->provider.dev = mc->dev; + mc->provider.data = &mc->provider; + mc->provider.set = mc->soc->icc_ops->set; + mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < mc->soc->num_clients; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + } + + /* + * MC driver is registered too early, so early that generic driver + * syncing doesn't work for the MC. But it doesn't really matter + * since syncing works for the EMC drivers, hence we can sync the + * MC driver by ourselves and then EMC will complete syncing of + * the whole ICC state. + */ + icc_sync_state(mc->dev); + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -727,6 +822,11 @@ static int tegra_mc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + err = tegra_mc_interconnect_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); if (IS_ERR(mc->smmu)) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..33e40d600592 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -78,6 +78,20 @@ #define MC_TIMING_UPDATE BIT(0) +static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) +{ + val = val * percents; + do_div(val, 100); + + return min_t(u64, val, U32_MAX); +} + +static inline struct tegra_mc * +icc_provider_to_tegra_mc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_mc, provider); +} + static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -115,4 +129,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra ICC drivers. The ID numbers are + * chosen such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_MC 1000 +#define TEGRA_ICC_EMC 1001 +#define TEGRA_ICC_EMEM 1002 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d9395af98143..43876216de34 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -6,7 +6,9 @@ #ifndef __SOC_TEGRA_MC_H__ #define __SOC_TEGRA_MC_H__ +#include <linux/bits.h> #include <linux/err.h> +#include <linux/interconnect-provider.h> #include <linux/reset-controller.h> #include <linux/types.h> @@ -141,6 +143,17 @@ struct tegra_mc_reset_ops { const struct tegra_mc_reset *rst); }; +#define TEGRA_MC_ICC_TAG_DEFAULT 0 +#define TEGRA_MC_ICC_TAG_ISO BIT(0) + +struct tegra_mc_icc_ops { + int (*set)(struct icc_node *src, struct icc_node *dst); + int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, + void *data); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -160,6 +173,8 @@ struct tegra_mc_soc { const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; unsigned int num_resets; + + const struct tegra_mc_icc_ops *icc_ops; }; struct tegra_mc { @@ -178,6 +193,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; -- 2.27.0 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-11-04 16:52 UTC|newest] Thread overview: 188+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-04 16:48 [PATCH v7 00/47] Introduce memory interconnect for NVIDIA Tegra SoCs Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 01/47] clk: tegra: Export Tegra20 EMC kernel symbols Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:23 ` Krzysztof Kozlowski 2020-11-06 18:23 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 02/47] soc/tegra: fuse: Export tegra_read_ram_code() Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:24 ` Krzysztof Kozlowski 2020-11-06 18:24 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 03/47] soc/tegra: fuse: Add stub for tegra_sku_info Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:25 ` Krzysztof Kozlowski 2020-11-06 18:25 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 04/47] dt-bindings: memory: tegra20: emc: Correct registers range in example Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:28 ` Krzysztof Kozlowski 2020-11-06 18:28 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Dmitry Osipenko 2020-11-06 18:29 ` [PATCH v7 05/47] dt-bindings: memory: tegra20: emc: Document nvidia,memory-controller property Krzysztof Kozlowski 2020-11-06 18:29 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 06/47] dt-bindings: memory: tegra20: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 07/47] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-06 18:30 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 08/47] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-05 19:48 ` Rob Herring 2020-11-05 19:48 ` Rob Herring 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 09/47] dt-bindings: memory: tegra30: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 10/47] dt-bindings: memory: tegra30: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-06 18:31 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 11/47] dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:32 ` Krzysztof Kozlowski 2020-11-06 18:32 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 12/47] dt-bindings: memory: tegra124: mc: Document new interconnect property Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-05 19:49 ` Rob Herring 2020-11-05 19:49 ` Rob Herring 2020-11-06 18:33 ` Krzysztof Kozlowski 2020-11-06 18:33 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 13/47] dt-bindings: memory: tegra124: emc: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 14/47] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 15/47] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-06 18:34 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 16/47] dt-bindings: host1x: Document new " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-06 18:36 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 17/47] dt-bindings: memory: tegra20: Add memory client IDs Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-26 17:26 ` Thierry Reding 2020-11-26 17:26 ` Thierry Reding 2020-11-26 17:39 ` Krzysztof Kozlowski 2020-11-26 17:39 ` Krzysztof Kozlowski 2020-11-26 17:45 ` Krzysztof Kozlowski 2020-11-26 17:45 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:59 ` Thierry Reding 2020-11-26 17:59 ` Thierry Reding 2020-11-26 18:02 ` Thierry Reding 2020-11-26 18:02 ` Thierry Reding 2020-11-26 18:06 ` Krzysztof Kozlowski 2020-11-26 18:06 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 18/47] dt-bindings: memory: tegra30: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-06 18:38 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 19/47] dt-bindings: memory: tegra124: " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-06 18:39 ` Krzysztof Kozlowski 2020-11-06 18:39 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-26 17:55 ` Krzysztof Kozlowski 2020-11-04 16:48 ` [PATCH v7 20/47] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 21/47] ARM: tegra: Add interconnect properties to " Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 22/47] ARM: tegra: Add interconnect properties to Tegra30 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:48 ` [PATCH v7 23/47] ARM: tegra: Add interconnect properties to Tegra124 device-tree Dmitry Osipenko 2020-11-04 16:48 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 24/47] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 24/47] ARM: tegra: Add nvidia, memory-controller " Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 25/47] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 26/47] ARM: tegra: Add DVFS properties to Tegra30 EMC and ACTMON device-tree nodes Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 27/47] ARM: tegra: Add DVFS properties to Tegra124 " Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 28/47] memory: tegra: Add and use devm_tegra_memory_controller_get() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:02 ` Krzysztof Kozlowski 2020-11-06 19:02 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 29/47] memory: tegra: Use devm_platform_ioremap_resource() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:03 ` Krzysztof Kozlowski 2020-11-06 19:03 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 30/47] memory: tegra: Remove superfluous error messages around platform_get_irq() Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:04 ` Krzysztof Kozlowski 2020-11-06 19:04 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 31/47] memory: tegra: Add missing latency allowness entry for Page Table Cache Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:05 ` Krzysztof Kozlowski 2020-11-06 19:05 ` Krzysztof Kozlowski 2020-11-04 16:49 ` Dmitry Osipenko [this message] 2020-11-04 16:49 ` [PATCH v7 32/47] memory: tegra-mc: Add interconnect framework Dmitry Osipenko 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 33/47] memory: tegra20-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-06 19:07 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 34/47] memory: tegra20-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:08 ` Krzysztof Kozlowski 2020-11-06 19:08 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 35/47] memory: tegra20: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-06 19:10 ` Krzysztof Kozlowski 2020-11-06 19:10 ` Krzysztof Kozlowski 2020-11-04 16:49 ` [PATCH v7 36/47] memory: tegra20-emc: Add devfreq support Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:30 ` Chanwoo Choi 2020-11-05 2:30 ` Chanwoo Choi 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-06 19:13 ` Krzysztof Kozlowski 2020-11-06 19:13 ` Krzysztof Kozlowski 2020-11-06 21:53 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 37/47] memory: tegra30: Add FIFO sizes to memory clients Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 38/47] memory: tegra30-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 39/47] memory: tegra30-emc: Continue probing if timings are missing in device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 40/47] memory: tegra30: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 41/47] memory: tegra124-emc: Make driver modular Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 42/47] memory: tegra124: Support interconnect framework Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 43/47] drm/tegra: dc: Support memory bandwidth management Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-09 4:02 ` kernel test robot 2020-11-04 16:49 ` [PATCH v7 44/47] drm/tegra: dc: Extend debug stats with total number of events Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-04 16:49 ` [PATCH v7 45/47] PM / devfreq: tegra30: Support interconnect and OPPs from device-tree Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:22 ` Chanwoo Choi 2020-11-05 2:22 ` Chanwoo Choi 2020-11-04 16:49 ` [PATCH v7 46/47] PM / devfreq: tegra30: Separate configurations per-SoC generation Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:23 ` Chanwoo Choi 2020-11-05 2:23 ` Chanwoo Choi 2020-11-04 16:49 ` [PATCH v7 47/47] PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver Dmitry Osipenko 2020-11-04 16:49 ` Dmitry Osipenko 2020-11-05 2:25 ` Chanwoo Choi 2020-11-05 2:25 ` Chanwoo Choi 2020-11-05 13:50 ` Dmitry Osipenko 2020-11-05 13:50 ` Dmitry Osipenko
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