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From: Michael Walle <michael@walle.cc>
To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
	"Y . b . Lu" <yangbo.lu@nxp.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	Ashish Kumar <Ashish.Kumar@nxp.com>,
	Vladimir Oltean <vladimir.oltean@nxp.com>,
	Michael Walle <michael@walle.cc>
Subject: [PATCH v3 3/9] clk: qoriq: provide constants for the type
Date: Sun,  8 Nov 2020 19:51:07 +0100	[thread overview]
Message-ID: <20201108185113.31377-4-michael@walle.cc> (raw)
In-Reply-To: <20201108185113.31377-1-michael@walle.cc>

To avoid future mistakes in the device tree for the clockgen module, add
constants for the clockgen subtype as well as a macro for the PLL
divider.

Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
 - new patch

 drivers/clk/clk-qoriq.c                        | 13 +++++++------
 include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
 2 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 46101c6a20f2..70aa521e7e7f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -7,6 +7,7 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
@@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
 	idx = clkspec->args[1];
 
 	switch (type) {
-	case 0:
+	case QORIQ_CLK_SYSCLK:
 		if (idx != 0)
 			goto bad_args;
 		clk = cg->sysclk;
 		break;
-	case 1:
+	case QORIQ_CLK_CMUX:
 		if (idx >= ARRAY_SIZE(cg->cmux))
 			goto bad_args;
 		clk = cg->cmux[idx];
 		break;
-	case 2:
+	case QORIQ_CLK_HWACCEL:
 		if (idx >= ARRAY_SIZE(cg->hwaccel))
 			goto bad_args;
 		clk = cg->hwaccel[idx];
 		break;
-	case 3:
+	case QORIQ_CLK_FMAN:
 		if (idx >= ARRAY_SIZE(cg->fman))
 			goto bad_args;
 		clk = cg->fman[idx];
 		break;
-	case 4:
+	case QORIQ_CLK_PLATFORM_PLL:
 		pll = &cg->pll[PLATFORM_PLL];
 		if (idx >= ARRAY_SIZE(pll->div))
 			goto bad_args;
 		clk = pll->div[idx].clk;
 		break;
-	case 5:
+	case QORIQ_CLK_CORECLK:
 		if (idx != 0)
 			goto bad_args;
 		clk = cg->coreclk;
diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
new file mode 100644
index 000000000000..ddec7d0bdc7f
--- /dev/null
+++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK	0
+#define QORIQ_CLK_CMUX		1
+#define QORIQ_CLK_HWACCEL	2
+#define QORIQ_CLK_FMAN		3
+#define QORIQ_CLK_PLATFORM_PLL	4
+#define QORIQ_CLK_CORECLK	5
+
+#define QORIQ_CLK_PLL_DIV(x)	((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc>
To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Vladimir Oltean <vladimir.oltean@nxp.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Ashish Kumar <Ashish.Kumar@nxp.com>, Li Yang <leoyang.li@nxp.com>,
	Michael Walle <michael@walle.cc>,
	Rob Herring <robh+dt@kernel.org>,
	"Y . b . Lu" <yangbo.lu@nxp.com>, Shawn Guo <shawnguo@kernel.org>
Subject: [PATCH v3 3/9] clk: qoriq: provide constants for the type
Date: Sun,  8 Nov 2020 19:51:07 +0100	[thread overview]
Message-ID: <20201108185113.31377-4-michael@walle.cc> (raw)
In-Reply-To: <20201108185113.31377-1-michael@walle.cc>

To avoid future mistakes in the device tree for the clockgen module, add
constants for the clockgen subtype as well as a macro for the PLL
divider.

Signed-off-by: Michael Walle <michael@walle.cc>
---
Changes since v2:
 - new patch

 drivers/clk/clk-qoriq.c                        | 13 +++++++------
 include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +++++++++++++++
 2 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 46101c6a20f2..70aa521e7e7f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -7,6 +7,7 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
@@ -1368,33 +1369,33 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
 	idx = clkspec->args[1];
 
 	switch (type) {
-	case 0:
+	case QORIQ_CLK_SYSCLK:
 		if (idx != 0)
 			goto bad_args;
 		clk = cg->sysclk;
 		break;
-	case 1:
+	case QORIQ_CLK_CMUX:
 		if (idx >= ARRAY_SIZE(cg->cmux))
 			goto bad_args;
 		clk = cg->cmux[idx];
 		break;
-	case 2:
+	case QORIQ_CLK_HWACCEL:
 		if (idx >= ARRAY_SIZE(cg->hwaccel))
 			goto bad_args;
 		clk = cg->hwaccel[idx];
 		break;
-	case 3:
+	case QORIQ_CLK_FMAN:
 		if (idx >= ARRAY_SIZE(cg->fman))
 			goto bad_args;
 		clk = cg->fman[idx];
 		break;
-	case 4:
+	case QORIQ_CLK_PLATFORM_PLL:
 		pll = &cg->pll[PLATFORM_PLL];
 		if (idx >= ARRAY_SIZE(pll->div))
 			goto bad_args;
 		clk = pll->div[idx].clk;
 		break;
-	case 5:
+	case QORIQ_CLK_CORECLK:
 		if (idx != 0)
 			goto bad_args;
 		clk = cg->coreclk;
diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
new file mode 100644
index 000000000000..ddec7d0bdc7f
--- /dev/null
+++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK	0
+#define QORIQ_CLK_CMUX		1
+#define QORIQ_CLK_HWACCEL	2
+#define QORIQ_CLK_FMAN		3
+#define QORIQ_CLK_PLATFORM_PLL	4
+#define QORIQ_CLK_CORECLK	5
+
+#define QORIQ_CLK_PLL_DIV(x)	((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
-- 
2.20.1


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  parent reply	other threads:[~2020-11-08 18:51 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-08 18:51 [PATCH v3 0/9] clk: qoriq fixes and new fsl-flexspi driver Michael Walle
2020-11-08 18:51 ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 1/9] arm64: dts: ls1028a: fix ENETC PTP clock input Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-11-30  9:20   ` Shawn Guo
2020-11-30  9:20     ` Shawn Guo
2020-11-08 18:51 ` [PATCH v3 2/9] arm64: dts: ls1028a: fix FlexSPI " Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-11-30  9:21   ` Shawn Guo
2020-11-30  9:21     ` Shawn Guo
2020-11-08 18:51 ` Michael Walle [this message]
2020-11-08 18:51   ` [PATCH v3 3/9] clk: qoriq: provide constants for the type Michael Walle
2020-11-09 22:05   ` Rob Herring
2020-11-09 22:05     ` Rob Herring
2020-11-09 22:39     ` Michael Walle
2020-11-09 22:39       ` Michael Walle
2020-11-09 22:55       ` Rob Herring
2020-11-09 22:55         ` Rob Herring
2020-12-08  0:54   ` Stephen Boyd
2020-11-08 18:51 ` [PATCH v3 4/9] arm64: dts: ls1028a: use constants in the clockgen phandle Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-11-20  9:25   ` [EXT] " Ashish Kumar
2020-11-20  9:25     ` Ashish Kumar
2020-11-20  9:38     ` Michael Walle
2020-11-20  9:38       ` Michael Walle
2020-11-20  9:51       ` [EXT] " Ashish Kumar
2020-11-20  9:51         ` Ashish Kumar
2020-11-20 10:05         ` Michael Walle
2020-11-20 10:05           ` Michael Walle
2020-11-08 18:51 ` [PATCH v3 5/9] clk: divider: add devm_clk_hw_register_divider_table() Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-12-08  0:54   ` Stephen Boyd
2020-11-08 18:51 ` [PATCH v3 6/9] dt-bindings: clock: document the fsl-flexspi-clk driver Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-12-08  0:54   ` Stephen Boyd
2020-11-08 18:51 ` [PATCH v3 7/9] clk: fsl-flexspi: new driver Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-12-08  0:58   ` Stephen Boyd
2020-11-08 18:51 ` [PATCH v3 8/9] arm64: dts: ls1028a: fix FlexSPI clock Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-11-08 18:51 ` [RFC PATCH v3 9/9] arm64: dts: lx2160a: " Michael Walle
2020-11-08 18:51   ` Michael Walle
2020-11-08 21:21   ` Vladimir Oltean
2020-11-08 21:21     ` Vladimir Oltean
2020-11-09  9:43     ` Michael Walle
2020-11-09  9:43       ` Michael Walle

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