From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, leo.yan@linaro.org, mike.leach@linaro.org, anshuman.khandual@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v6 15/26] coresight: etm4x: Handle ETM architecture version Date: Thu, 7 Jan 2021 12:38:48 +0000 [thread overview] Message-ID: <20210107123859.674252-16-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210107123859.674252-1-suzuki.poulose@arm.com> We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 60 ++++++++++++++++++- 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 8d696c0aef0d..6e38b1592b5d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -917,7 +917,7 @@ static void etm4_init_arch_data(void *info) * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ drvdata->nr_resource = BMVAL(etmidr4, 16, 19); - if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0)) + if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) drvdata->nr_resource += 1; /* * NUMSSCC, bits[23:20] the number of single-shot diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 841a3fe88f39..f68b2f8a6919 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -461,7 +461,6 @@ #define ETM_MAX_RES_SEL 32 #define ETM_MAX_SS_CMP 8 -#define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF #define ETM_CYC_THRESHOLD_DEFAULT 0x100 @@ -586,8 +585,63 @@ #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 +#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 +#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT +#define ETM_TRCIDR1_ARCH_MASK \ + (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) + +#define ETM_TRCIDR1_ARCH_ETMv4 0x4 + +/* + * Driver representation of the ETM architecture. + * The version of an ETM component can be detected from + * + * TRCDEVARCH - CoreSight architected register + * - Bits[15:12] - Major version + * - Bits[19:16] - Minor version + * TRCIDR1 - ETM architected register + * - Bits[11:8] - Major version + * - Bits[7:4] - Minor version + * We must rely on TRCDEVARCH for the version information, + * however we don't want to break the support for potential + * old implementations which might not implement it. Thus + * we fall back to TRCIDR1 if TRCDEVARCH is not implemented + * for memory mapped components. + * Now to make certain decisions easier based on the version + * we use an internal representation of the version in the + * driver, as follows : + * + * ETM_ARCH_VERSION[7:0], where : + * Bits[7:4] - Major version + * Bits[3:0] - Minro version + */ +#define ETM_ARCH_VERSION(major, minor) \ + ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) +#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) +#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) + +#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) /* Interpretation of resource numbers change at ETM v4.3 architecture */ -#define ETM4X_ARCH_4V3 0x43 +#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) + +static inline u8 etm_devarch_to_arch(u32 devarch) +{ + return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), + ETM_DEVARCH_REVISION(devarch)); +} + +static inline u8 etm_trcidr_to_arch(u32 trcidr1) +{ + return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), + ETM_TRCIDR1_ARCH_MINOR(trcidr1)); +} enum etm_impdef_type { ETM4_IMPDEF_HISI_CORE_COMMIT, @@ -754,7 +808,7 @@ struct etmv4_save_state { * @spinlock: Only one at a time pls. * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. - * @arch: ETM version number. + * @arch: ETM architecture version. * @nr_pe: The number of processing entity available for tracing. * @nr_pe_cmp: The number of processing entity comparator inputs that are * available for tracing. -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>, linux-kernel@vger.kernel.org, leo.yan@linaro.org, mike.leach@linaro.org Subject: [PATCH v6 15/26] coresight: etm4x: Handle ETM architecture version Date: Thu, 7 Jan 2021 12:38:48 +0000 [thread overview] Message-ID: <20210107123859.674252-16-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210107123859.674252-1-suzuki.poulose@arm.com> We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 60 ++++++++++++++++++- 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 8d696c0aef0d..6e38b1592b5d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -917,7 +917,7 @@ static void etm4_init_arch_data(void *info) * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ drvdata->nr_resource = BMVAL(etmidr4, 16, 19); - if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0)) + if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) drvdata->nr_resource += 1; /* * NUMSSCC, bits[23:20] the number of single-shot diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 841a3fe88f39..f68b2f8a6919 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -461,7 +461,6 @@ #define ETM_MAX_RES_SEL 32 #define ETM_MAX_SS_CMP 8 -#define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF #define ETM_CYC_THRESHOLD_DEFAULT 0x100 @@ -586,8 +585,63 @@ #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 +#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 +#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT +#define ETM_TRCIDR1_ARCH_MASK \ + (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) + +#define ETM_TRCIDR1_ARCH_ETMv4 0x4 + +/* + * Driver representation of the ETM architecture. + * The version of an ETM component can be detected from + * + * TRCDEVARCH - CoreSight architected register + * - Bits[15:12] - Major version + * - Bits[19:16] - Minor version + * TRCIDR1 - ETM architected register + * - Bits[11:8] - Major version + * - Bits[7:4] - Minor version + * We must rely on TRCDEVARCH for the version information, + * however we don't want to break the support for potential + * old implementations which might not implement it. Thus + * we fall back to TRCIDR1 if TRCDEVARCH is not implemented + * for memory mapped components. + * Now to make certain decisions easier based on the version + * we use an internal representation of the version in the + * driver, as follows : + * + * ETM_ARCH_VERSION[7:0], where : + * Bits[7:4] - Major version + * Bits[3:0] - Minro version + */ +#define ETM_ARCH_VERSION(major, minor) \ + ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) +#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) +#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) + +#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) /* Interpretation of resource numbers change at ETM v4.3 architecture */ -#define ETM4X_ARCH_4V3 0x43 +#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) + +static inline u8 etm_devarch_to_arch(u32 devarch) +{ + return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), + ETM_DEVARCH_REVISION(devarch)); +} + +static inline u8 etm_trcidr_to_arch(u32 trcidr1) +{ + return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), + ETM_TRCIDR1_ARCH_MINOR(trcidr1)); +} enum etm_impdef_type { ETM4_IMPDEF_HISI_CORE_COMMIT, @@ -754,7 +808,7 @@ struct etmv4_save_state { * @spinlock: Only one at a time pls. * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. - * @arch: ETM version number. + * @arch: ETM architecture version. * @nr_pe: The number of processing entity available for tracing. * @nr_pe_cmp: The number of processing entity comparator inputs that are * available for tracing. -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-07 12:41 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-07 12:38 [PATCH v6 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 01/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 02/26] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 03/26] coresight: Introduce device access abstraction Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 23:38 ` Mathieu Poirier 2021-01-07 23:38 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 04/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 05/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 06/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 07/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 08/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 09/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 10/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 11/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 12/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 0:18 ` Mathieu Poirier 2021-01-08 0:18 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 13/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 14/26] coresight: etm4x: Clean up " Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose [this message] 2021-01-07 12:38 ` [PATCH v6 15/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 16/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 17/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 18/26] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 19/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 20/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 21/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 0:38 ` Mathieu Poirier 2021-01-08 0:38 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 22/26] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 0:49 ` Mathieu Poirier 2021-01-08 0:49 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 23/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 0:55 ` Mathieu Poirier 2021-01-08 0:55 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 24/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-07 12:38 ` [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 1:01 ` Mathieu Poirier 2021-01-08 1:01 ` Mathieu Poirier 2021-01-07 12:38 ` [PATCH v6 26/26] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose 2021-01-07 12:38 ` Suzuki K Poulose 2021-01-08 1:02 ` Mathieu Poirier 2021-01-08 1:02 ` Mathieu Poirier 2021-01-08 1:09 ` [PATCH v6 00/26] coresight: etm4x: Support for system instructions Mathieu Poirier 2021-01-08 1:09 ` Mathieu Poirier 2021-01-08 9:08 ` Suzuki K Poulose 2021-01-08 9:08 ` Suzuki K Poulose 2021-01-08 14:15 ` Suzuki K Poulose 2021-01-08 14:15 ` Suzuki K Poulose
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