From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@siol.net> Cc: "Icenowy Zheng" <icenowy@aosc.io>, "Linus Walleij" <linus.walleij@linaro.org>, "Rob Herring" <robh@kernel.org>, "Clément Péron" <peron.clem@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Shuosheng Huang" <huangshuosheng@allwinnertech.com>, "Yangtao Li" <tiny.windzz@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, "Kishon Vijay Abraham I" <kishon@ti.com>, "Vinod Koul" <vkoul@kernel.org> Subject: [PATCH v3 13/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Date: Mon, 18 Jan 2021 02:08:40 +0000 [thread overview] Message-ID: <20210118020848.11721-14-andre.przywara@arm.com> (raw) In-Reply-To: <20210118020848.11721-1-andre.przywara@arm.com> As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++++++++++---------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 788dd5cdbb7d..539209fe3468 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -43,7 +43,7 @@ #define REG_PHYCTL_A33 0x10 #define REG_PHY_OTGCTL 0x20 -#define REG_PMU_UNK1 0x10 +#define REG_HCI_PHY_CTL 0x10 #define PHYCTL_DATA BIT(7) @@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg { int hsic_index; enum sun4i_usb_phy_type type; u32 disc_thresh; + u32 hci_phy_ctl_siddq; u8 phyctl_offset; bool dedicated_clocks; - bool enable_pmu_unk1; bool phy0_dual_route; int missing_phys; }; @@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } + if (phy->pmu && data->cfg->hci_phy_ctl_siddq) { + val = readl(phy->pmu + REG_HCI_PHY_CTL); + val &= ~data->cfg->hci_phy_ctl_siddq; + writel(val, phy->pmu + REG_HCI_PHY_CTL); + } + if (data->cfg->type == sun8i_a83t_phy || data->cfg->type == sun50i_h6_phy) { if (phy->index == 0) { @@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, data->base + data->cfg->phyctl_offset); } } else { - if (phy->pmu && data->cfg->enable_pmu_unk1) { - val = readl(phy->pmu + REG_PMU_UNK1); - writel(val & ~2, phy->pmu + REG_PMU_UNK1); - } - /* Enable USB 45 Ohm resistor calibration */ if (phy->index == 0) sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); @@ -863,7 +864,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { @@ -872,7 +872,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { @@ -881,7 +880,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { @@ -890,7 +888,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { @@ -899,7 +896,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { @@ -908,7 +904,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { @@ -925,7 +920,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -935,7 +930,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -945,7 +940,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -955,7 +950,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; -- 2.17.5
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@siol.net> Cc: "Vinod Koul" <vkoul@kernel.org>, "Samuel Holland" <samuel@sholland.org>, "Yangtao Li" <tiny.windzz@gmail.com>, "Linus Walleij" <linus.walleij@linaro.org>, linux-kernel@vger.kernel.org, "Kishon Vijay Abraham I" <kishon@ti.com>, linux-sunxi@googlegroups.com, "Clément Péron" <peron.clem@gmail.com>, "Shuosheng Huang" <huangshuosheng@allwinnertech.com>, linux-arm-kernel@lists.infradead.org, "Icenowy Zheng" <icenowy@aosc.io> Subject: [PATCH v3 13/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Date: Mon, 18 Jan 2021 02:08:40 +0000 [thread overview] Message-ID: <20210118020848.11721-14-andre.przywara@arm.com> (raw) In-Reply-To: <20210118020848.11721-1-andre.przywara@arm.com> As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++++++++++---------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 788dd5cdbb7d..539209fe3468 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -43,7 +43,7 @@ #define REG_PHYCTL_A33 0x10 #define REG_PHY_OTGCTL 0x20 -#define REG_PMU_UNK1 0x10 +#define REG_HCI_PHY_CTL 0x10 #define PHYCTL_DATA BIT(7) @@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg { int hsic_index; enum sun4i_usb_phy_type type; u32 disc_thresh; + u32 hci_phy_ctl_siddq; u8 phyctl_offset; bool dedicated_clocks; - bool enable_pmu_unk1; bool phy0_dual_route; int missing_phys; }; @@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } + if (phy->pmu && data->cfg->hci_phy_ctl_siddq) { + val = readl(phy->pmu + REG_HCI_PHY_CTL); + val &= ~data->cfg->hci_phy_ctl_siddq; + writel(val, phy->pmu + REG_HCI_PHY_CTL); + } + if (data->cfg->type == sun8i_a83t_phy || data->cfg->type == sun50i_h6_phy) { if (phy->index == 0) { @@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, data->base + data->cfg->phyctl_offset); } } else { - if (phy->pmu && data->cfg->enable_pmu_unk1) { - val = readl(phy->pmu + REG_PMU_UNK1); - writel(val & ~2, phy->pmu + REG_PMU_UNK1); - } - /* Enable USB 45 Ohm resistor calibration */ if (phy->index == 0) sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); @@ -863,7 +864,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { @@ -872,7 +872,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { @@ -881,7 +880,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { @@ -890,7 +888,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { @@ -899,7 +896,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { @@ -908,7 +904,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { @@ -925,7 +920,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -935,7 +930,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -945,7 +940,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; @@ -955,7 +950,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_siddq = BIT(1), .phy0_dual_route = true, }; -- 2.17.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-18 2:13 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-18 2:08 [PATCH v3 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 01/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 13:28 ` Maxime Ripard 2021-01-18 13:28 ` Maxime Ripard 2021-01-18 15:52 ` Andre Przywara 2021-01-18 15:52 ` Andre Przywara 2021-01-18 15:55 ` [linux-sunxi] " Chen-Yu Tsai 2021-01-18 15:55 ` Chen-Yu Tsai 2021-01-21 16:38 ` Maxime Ripard 2021-01-21 16:38 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 03/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 13:29 ` Maxime Ripard 2021-01-18 13:29 ` Maxime Ripard 2021-01-21 21:12 ` Linus Walleij 2021-01-21 21:12 ` Linus Walleij 2021-01-18 2:08 ` [PATCH v3 04/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:26 ` Maxime Ripard 2021-01-18 15:26 ` Maxime Ripard 2021-01-21 21:14 ` Linus Walleij 2021-01-21 21:14 ` Linus Walleij 2021-01-18 2:08 ` [PATCH v3 05/21] pinctrl: sunxi: Add support for the Allwinner H616-R " Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-21 21:16 ` Linus Walleij 2021-01-21 21:16 ` Linus Walleij 2021-01-18 2:08 ` [PATCH v3 06/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:26 ` Maxime Ripard 2021-01-18 15:26 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 07/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:30 ` Maxime Ripard 2021-01-18 15:30 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 08/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:30 ` Maxime Ripard 2021-01-18 15:30 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 09/21] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 3:37 ` Samuel Holland 2021-01-18 3:37 ` Samuel Holland 2021-01-21 15:54 ` Andre Przywara 2021-01-21 15:54 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 10/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 11/21] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 12/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 21:27 ` Jakub Kicinski 2021-01-18 21:27 ` Jakub Kicinski 2021-01-18 2:08 ` Andre Przywara [this message] 2021-01-18 2:08 ` [PATCH v3 13/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara 2021-01-18 15:32 ` Maxime Ripard 2021-01-18 15:32 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 14/21] dt-bindings: usb: Add H616 compatible string Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 15/21] dt-bindings: usb: sunxi-musb: " Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 16/21] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 15:33 ` Maxime Ripard 2021-01-18 2:08 ` [PATCH v3 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 15:34 ` maxime 2021-01-18 15:34 ` maxime 2021-01-23 17:31 ` Guenter Roeck 2021-01-23 17:31 ` Guenter Roeck 2021-01-18 2:08 ` [PATCH v3 18/21] dt-bindings: allwinner: Add H616 compatible strings Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 4:28 ` Samuel Holland 2021-01-18 4:28 ` Samuel Holland 2021-01-25 11:59 ` Andre Przywara 2021-01-25 11:59 ` Andre Przywara 2021-01-18 12:05 ` Mark Brown 2021-01-18 12:05 ` Mark Brown 2021-01-18 2:08 ` [PATCH v3 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 4:35 ` Samuel Holland 2021-01-18 4:35 ` Samuel Holland 2021-01-18 2:08 ` [PATCH v3 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara 2021-01-18 2:08 ` Andre Przywara 2021-01-18 2:08 ` [PATCH v3 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara 2021-01-18 2:08 ` Andre Przywara
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