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From: Zhen Lei <thunder.leizhen@huawei.com>
To: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	"Mark Rutland" <mark.rutland@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	iommu <iommu@lists.linux-foundation.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Cc: Zhen Lei <thunder.leizhen@huawei.com>,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Subject: [PATCH v3 1/3] perf/smmuv3: Don't reserve the PMCG register spaces
Date: Wed, 27 Jan 2021 19:32:56 +0800	[thread overview]
Message-ID: <20210127113258.1421-2-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <20210127113258.1421-1-thunder.leizhen@huawei.com>

According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.

This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.

To avoid this conflict, don't reserve the PMCG regions.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/perf/arm_smmuv3_pmu.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..e5e505a0804fe53 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,29 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
 	dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
 }
 
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+				  unsigned int index,
+				  struct resource **res)
+{
+	void __iomem *base;
+	struct resource *r;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, index);
+	if (!r) {
+		dev_err(&pdev->dev, "invalid resource\n");
+		return ERR_PTR(-EINVAL);
+	}
+	if (res)
+		*res = r;
+
+	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!base)
+		return ERR_PTR(-ENOMEM);
+
+	return base;
+}
+
 static int smmu_pmu_probe(struct platform_device *pdev)
 {
 	struct smmu_pmu *smmu_pmu;
@@ -793,7 +816,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
 	};
 
-	smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
+	smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, &res_0);
 	if (IS_ERR(smmu_pmu->reg_base))
 		return PTR_ERR(smmu_pmu->reg_base);
 
@@ -801,7 +824,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 
 	/* Determine if page 1 is present */
 	if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
-		smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+		smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev, 1, NULL);
 		if (IS_ERR(smmu_pmu->reloc_base))
 			return PTR_ERR(smmu_pmu->reloc_base);
 	} else {
-- 
1.8.3



WARNING: multiple messages have this Message-ID (diff)
From: Zhen Lei <thunder.leizhen@huawei.com>
To: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	"Mark Rutland" <mark.rutland@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	iommu <iommu@lists.linux-foundation.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: [PATCH v3 1/3] perf/smmuv3: Don't reserve the PMCG register spaces
Date: Wed, 27 Jan 2021 19:32:56 +0800	[thread overview]
Message-ID: <20210127113258.1421-2-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <20210127113258.1421-1-thunder.leizhen@huawei.com>

According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.

This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.

To avoid this conflict, don't reserve the PMCG regions.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/perf/arm_smmuv3_pmu.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..e5e505a0804fe53 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,29 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
 	dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
 }
 
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+				  unsigned int index,
+				  struct resource **res)
+{
+	void __iomem *base;
+	struct resource *r;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, index);
+	if (!r) {
+		dev_err(&pdev->dev, "invalid resource\n");
+		return ERR_PTR(-EINVAL);
+	}
+	if (res)
+		*res = r;
+
+	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!base)
+		return ERR_PTR(-ENOMEM);
+
+	return base;
+}
+
 static int smmu_pmu_probe(struct platform_device *pdev)
 {
 	struct smmu_pmu *smmu_pmu;
@@ -793,7 +816,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
 	};
 
-	smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
+	smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, &res_0);
 	if (IS_ERR(smmu_pmu->reg_base))
 		return PTR_ERR(smmu_pmu->reg_base);
 
@@ -801,7 +824,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 
 	/* Determine if page 1 is present */
 	if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
-		smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+		smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev, 1, NULL);
 		if (IS_ERR(smmu_pmu->reloc_base))
 			return PTR_ERR(smmu_pmu->reloc_base);
 	} else {
-- 
1.8.3


_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Zhen Lei <thunder.leizhen@huawei.com>
To: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	"Mark Rutland" <mark.rutland@arm.com>,
	Joerg Roedel <joro@8bytes.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	iommu <iommu@lists.linux-foundation.org>,
	linux-kernel <linux-kernel@vger.kernel.org>
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	Zhen Lei <thunder.leizhen@huawei.com>
Subject: [PATCH v3 1/3] perf/smmuv3: Don't reserve the PMCG register spaces
Date: Wed, 27 Jan 2021 19:32:56 +0800	[thread overview]
Message-ID: <20210127113258.1421-2-thunder.leizhen@huawei.com> (raw)
In-Reply-To: <20210127113258.1421-1-thunder.leizhen@huawei.com>

According to the SMMUv3 specification:
Each PMCG counter group is represented by one 4KB page (Page 0) with one
optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION
DEFINED base addresses.

This means that the PMCG register spaces may be within the 64KB pages of
the SMMUv3 register space. When both the SMMU and PMCG drivers reserve
their own resources, a resource conflict occurs.

To avoid this conflict, don't reserve the PMCG regions.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 drivers/perf/arm_smmuv3_pmu.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
index 74474bb322c3f26..e5e505a0804fe53 100644
--- a/drivers/perf/arm_smmuv3_pmu.c
+++ b/drivers/perf/arm_smmuv3_pmu.c
@@ -761,6 +761,29 @@ static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
 	dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
 }
 
+static void __iomem *
+smmu_pmu_get_and_ioremap_resource(struct platform_device *pdev,
+				  unsigned int index,
+				  struct resource **res)
+{
+	void __iomem *base;
+	struct resource *r;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, index);
+	if (!r) {
+		dev_err(&pdev->dev, "invalid resource\n");
+		return ERR_PTR(-EINVAL);
+	}
+	if (res)
+		*res = r;
+
+	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!base)
+		return ERR_PTR(-ENOMEM);
+
+	return base;
+}
+
 static int smmu_pmu_probe(struct platform_device *pdev)
 {
 	struct smmu_pmu *smmu_pmu;
@@ -793,7 +816,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 		.capabilities	= PERF_PMU_CAP_NO_EXCLUDE,
 	};
 
-	smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
+	smmu_pmu->reg_base = smmu_pmu_get_and_ioremap_resource(pdev, 0, &res_0);
 	if (IS_ERR(smmu_pmu->reg_base))
 		return PTR_ERR(smmu_pmu->reg_base);
 
@@ -801,7 +824,7 @@ static int smmu_pmu_probe(struct platform_device *pdev)
 
 	/* Determine if page 1 is present */
 	if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
-		smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
+		smmu_pmu->reloc_base = smmu_pmu_get_and_ioremap_resource(pdev, 1, NULL);
 		if (IS_ERR(smmu_pmu->reloc_base))
 			return PTR_ERR(smmu_pmu->reloc_base);
 	} else {
-- 
1.8.3



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-01-27 11:36 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-27 11:32 [PATCH v3 0/3] perf/smmuv3: Don't reserve the PMCG register spaces Zhen Lei
2021-01-27 11:32 ` Zhen Lei
2021-01-27 11:32 ` Zhen Lei
2021-01-27 11:32 ` Zhen Lei [this message]
2021-01-27 11:32   ` [PATCH v3 1/3] " Zhen Lei
2021-01-27 11:32   ` Zhen Lei
2021-01-29 15:06   ` Robin Murphy
2021-01-29 15:06     ` Robin Murphy
2021-01-30  2:23     ` Leizhen (ThunderTown)
2021-01-30  2:23       ` Leizhen (ThunderTown)
2021-01-30  2:23       ` Leizhen (ThunderTown)
2021-01-27 11:32 ` [PATCH v3 2/3] perf/smmuv3: Add a MODULE_SOFTDEP() to indicate dependency on SMMU Zhen Lei
2021-01-27 11:32   ` Zhen Lei
2021-01-27 11:32   ` Zhen Lei
2021-01-29 15:12   ` Robin Murphy
2021-01-29 15:12     ` Robin Murphy
2021-01-29 15:34     ` John Garry
2021-01-29 15:34       ` John Garry
2021-01-29 17:03       ` Robin Murphy
2021-01-29 17:03         ` Robin Murphy
2021-01-29 17:03         ` Robin Murphy
2021-01-30  1:34         ` Leizhen (ThunderTown)
2021-01-30  1:34           ` Leizhen (ThunderTown)
2021-01-30  1:34           ` Leizhen (ThunderTown)
2021-01-27 11:32 ` [PATCH v3 3/3] iommu/arm-smmu-v3: Reserving the entire SMMU register space Zhen Lei
2021-01-27 11:32   ` Zhen Lei
2021-01-27 11:32   ` Zhen Lei
2021-01-29 15:27   ` Robin Murphy
2021-01-29 15:27     ` Robin Murphy
2021-01-30  1:54     ` Leizhen (ThunderTown)
2021-01-30  1:54       ` Leizhen (ThunderTown)
2021-01-30  1:54       ` Leizhen (ThunderTown)
2021-02-01 11:44       ` Robin Murphy
2021-02-01 11:44         ` Robin Murphy
2021-02-01 11:44         ` Robin Murphy
2021-02-01 12:00         ` Leizhen (ThunderTown)
2021-02-01 12:00           ` Leizhen (ThunderTown)
2021-02-01 12:00           ` Leizhen (ThunderTown)
2021-01-28 20:31 ` [PATCH v3 0/3] perf/smmuv3: Don't reserve the PMCG register spaces Will Deacon
2021-01-28 20:31   ` Will Deacon
2021-01-28 20:31   ` Will Deacon
2021-01-29 13:15   ` Leizhen (ThunderTown)
2021-01-29 13:15     ` Leizhen (ThunderTown)

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