From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU
Date: Mon, 1 Feb 2021 11:13:29 -0700 [thread overview]
Message-ID: <20210201181351.1475223-10-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../coresight/coresight-etm4x-sysfs.c | 23 ++++++++-----------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 989ce7b8ade7..c4781d4e5886 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2344,23 +2344,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset)
return reg.data;
}
-#define coresight_etm4x_reg(name, offset) \
- coresight_simple_reg32(struct etmv4_drvdata, name, offset)
-
#define coresight_etm4x_cross_read(name, offset) \
coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \
name, offset)
-coresight_etm4x_reg(trcpdcr, TRCPDCR);
-coresight_etm4x_reg(trcpdsr, TRCPDSR);
-coresight_etm4x_reg(trclsr, TRCLSR);
-coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS);
-coresight_etm4x_reg(trcdevid, TRCDEVID);
-coresight_etm4x_reg(trcdevtype, TRCDEVTYPE);
-coresight_etm4x_reg(trcpidr0, TRCPIDR0);
-coresight_etm4x_reg(trcpidr1, TRCPIDR1);
-coresight_etm4x_reg(trcpidr2, TRCPIDR2);
-coresight_etm4x_reg(trcpidr3, TRCPIDR3);
+coresight_etm4x_cross_read(trcpdcr, TRCPDCR);
+coresight_etm4x_cross_read(trcpdsr, TRCPDSR);
+coresight_etm4x_cross_read(trclsr, TRCLSR);
+coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS);
+coresight_etm4x_cross_read(trcdevid, TRCDEVID);
+coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE);
+coresight_etm4x_cross_read(trcpidr0, TRCPIDR0);
+coresight_etm4x_cross_read(trcpidr1, TRCPIDR1);
+coresight_etm4x_cross_read(trcpidr2, TRCPIDR2);
+coresight_etm4x_cross_read(trcpidr3, TRCPIDR3);
coresight_etm4x_cross_read(trcoslsr, TRCOSLSR);
coresight_etm4x_cross_read(trcconfig, TRCCONFIGR);
coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR);
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU
Date: Mon, 1 Feb 2021 11:13:29 -0700 [thread overview]
Message-ID: <20210201181351.1475223-10-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../coresight/coresight-etm4x-sysfs.c | 23 ++++++++-----------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 989ce7b8ade7..c4781d4e5886 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2344,23 +2344,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset)
return reg.data;
}
-#define coresight_etm4x_reg(name, offset) \
- coresight_simple_reg32(struct etmv4_drvdata, name, offset)
-
#define coresight_etm4x_cross_read(name, offset) \
coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \
name, offset)
-coresight_etm4x_reg(trcpdcr, TRCPDCR);
-coresight_etm4x_reg(trcpdsr, TRCPDSR);
-coresight_etm4x_reg(trclsr, TRCLSR);
-coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS);
-coresight_etm4x_reg(trcdevid, TRCDEVID);
-coresight_etm4x_reg(trcdevtype, TRCDEVTYPE);
-coresight_etm4x_reg(trcpidr0, TRCPIDR0);
-coresight_etm4x_reg(trcpidr1, TRCPIDR1);
-coresight_etm4x_reg(trcpidr2, TRCPIDR2);
-coresight_etm4x_reg(trcpidr3, TRCPIDR3);
+coresight_etm4x_cross_read(trcpdcr, TRCPDCR);
+coresight_etm4x_cross_read(trcpdsr, TRCPDSR);
+coresight_etm4x_cross_read(trclsr, TRCLSR);
+coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS);
+coresight_etm4x_cross_read(trcdevid, TRCDEVID);
+coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE);
+coresight_etm4x_cross_read(trcpidr0, TRCPIDR0);
+coresight_etm4x_cross_read(trcpidr1, TRCPIDR1);
+coresight_etm4x_cross_read(trcpidr2, TRCPIDR2);
+coresight_etm4x_cross_read(trcpidr3, TRCPIDR3);
coresight_etm4x_cross_read(trcoslsr, TRCOSLSR);
coresight_etm4x_cross_read(trcconfig, TRCCONFIGR);
coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR);
--
2.25.1
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next prev parent reply other threads:[~2021-02-01 18:42 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 18:13 [PATCH 00/31] coresight: Patches for v5.12 Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 01/31] coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 02/31] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 03/31] coresight: etm4x: Handle access to TRCSSPCICRn Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 04/31] coresight: etm4x: Skip accessing TRCPDCR in save/restore Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 05/31] coresight: Introduce device access abstraction Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 06/31] coresight: tpiu: Prepare for using coresight " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 07/31] coresight: Convert coresight_timeout to use " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 08/31] coresight: Convert claim/disclaim operations to use access wrappers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier [this message]
2021-02-01 18:13 ` [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU Mathieu Poirier
2021-02-01 18:13 ` [PATCH 10/31] coresight: etm4x: Convert all register accesses Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 11/31] coresight: etm4x: Make offset available for sysfs attributes Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 12/31] coresight: etm4x: Add commentary on the registers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 13/31] coresight: etm4x: Add sysreg access helpers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 14/31] coresight: etm4x: Hide sysfs attributes for unavailable registers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 15/31] coresight: etm4x: Define DEVARCH register fields Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 16/31] coresight: etm4x: Check for Software Lock Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 17/31] coresight: etm4x: Cleanup secure exception level masks Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 18/31] coresight: etm4x: Clean up " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 19/31] coresight: etm4x: Handle ETM architecture version Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 20/31] coresight: etm4x: Detect access early on the target CPU Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 21/31] coresight: etm4x: Use TRCDEVARCH for component discovery Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 22/31] coresight: etm4x: Expose trcdevarch via sysfs Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 23/31] coresight: etm4x: Add necessary synchronization for sysreg access Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 24/31] coresight: etm4x: Detect system instructions support Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 25/31] coresight: etm4x: Refactor probing routine Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 26/31] coresight: etm4x: Run arch feature detection on the CPU Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 27/31] coresight: etm4x: Add support for sysreg only devices Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 28/31] dts: bindings: coresight: ETM system register access only units Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 29/31] arm64: Add TRFCR_ELx definitions Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 30/31] coresight: Add support for v8.4 SelfHosted tracing Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 31/31] coresight: etm4x: Handle accesses to TRCSTALLCTLR Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-04 16:01 ` [PATCH 00/31] coresight: Patches for v5.12 Greg KH
2021-02-04 16:01 ` Greg KH
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