From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 29/31] arm64: Add TRFCR_ELx definitions
Date: Mon, 1 Feb 2021 11:13:49 -0700 [thread overview]
Message-ID: <20210201181351.1475223-30-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org>
From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ split the register definitions to separate patch
rename some of the symbols ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
arch/arm64/include/asm/sysreg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8b5e7e5c3cc8..4acff97519b9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -191,6 +191,7 @@
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
@@ -471,6 +472,7 @@
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
@@ -829,6 +831,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
@@ -1003,6 +1006,14 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
+#define TRFCR_ELx_TS_SHIFT 5
+#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX BIT(3)
+#define TRFCR_ELx_ExTRE BIT(1)
+#define TRFCR_ELx_E0TRE BIT(0)
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 29/31] arm64: Add TRFCR_ELx definitions
Date: Mon, 1 Feb 2021 11:13:49 -0700 [thread overview]
Message-ID: <20210201181351.1475223-30-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org>
From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
Add definitions for the Arm v8.4 SelfHosted trace extensions registers.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com>
[ split the register definitions to separate patch
rename some of the symbols ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
arch/arm64/include/asm/sysreg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8b5e7e5c3cc8..4acff97519b9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -191,6 +191,7 @@
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
#define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
+#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
@@ -471,6 +472,7 @@
#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
#define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
+#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
@@ -829,6 +831,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
@@ -1003,6 +1006,14 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
+#define TRFCR_ELx_TS_SHIFT 5
+#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
+#define TRFCR_EL2_CX BIT(3)
+#define TRFCR_ELx_ExTRE BIT(1)
+#define TRFCR_ELx_E0TRE BIT(0)
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
--
2.25.1
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next prev parent reply other threads:[~2021-02-01 18:22 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 18:13 [PATCH 00/31] coresight: Patches for v5.12 Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 01/31] coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 02/31] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 03/31] coresight: etm4x: Handle access to TRCSSPCICRn Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 04/31] coresight: etm4x: Skip accessing TRCPDCR in save/restore Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 05/31] coresight: Introduce device access abstraction Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 06/31] coresight: tpiu: Prepare for using coresight " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 07/31] coresight: Convert coresight_timeout to use " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 08/31] coresight: Convert claim/disclaim operations to use access wrappers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 10/31] coresight: etm4x: Convert all register accesses Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 11/31] coresight: etm4x: Make offset available for sysfs attributes Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 12/31] coresight: etm4x: Add commentary on the registers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 13/31] coresight: etm4x: Add sysreg access helpers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 14/31] coresight: etm4x: Hide sysfs attributes for unavailable registers Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 15/31] coresight: etm4x: Define DEVARCH register fields Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 16/31] coresight: etm4x: Check for Software Lock Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 17/31] coresight: etm4x: Cleanup secure exception level masks Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 18/31] coresight: etm4x: Clean up " Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 19/31] coresight: etm4x: Handle ETM architecture version Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 20/31] coresight: etm4x: Detect access early on the target CPU Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 21/31] coresight: etm4x: Use TRCDEVARCH for component discovery Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 22/31] coresight: etm4x: Expose trcdevarch via sysfs Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 23/31] coresight: etm4x: Add necessary synchronization for sysreg access Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 24/31] coresight: etm4x: Detect system instructions support Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 25/31] coresight: etm4x: Refactor probing routine Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 26/31] coresight: etm4x: Run arch feature detection on the CPU Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 27/31] coresight: etm4x: Add support for sysreg only devices Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 28/31] dts: bindings: coresight: ETM system register access only units Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier [this message]
2021-02-01 18:13 ` [PATCH 29/31] arm64: Add TRFCR_ELx definitions Mathieu Poirier
2021-02-01 18:13 ` [PATCH 30/31] coresight: Add support for v8.4 SelfHosted tracing Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-01 18:13 ` [PATCH 31/31] coresight: etm4x: Handle accesses to TRCSTALLCTLR Mathieu Poirier
2021-02-01 18:13 ` Mathieu Poirier
2021-02-04 16:01 ` [PATCH 00/31] coresight: Patches for v5.12 Greg KH
2021-02-04 16:01 ` Greg KH
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