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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v2 05/14] drm/i915: Convert DG1 over to .{enable, disable}_clock()
Date: Thu,  4 Feb 2021 20:10:39 +0200	[thread overview]
Message-ID: <20210204181048.24202-6-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ea408ff254b..cbeb75d00013 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3127,8 +3127,8 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
-				  const struct intel_crtc_state *crtc_state)
+static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -3161,6 +3161,19 @@ static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -3213,19 +3226,6 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
-static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
-{
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-
-	mutex_lock(&dev_priv->dpll.lock);
-
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
-
-	mutex_unlock(&dev_priv->dpll.lock);
-}
-
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -4007,9 +4007,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (IS_DG1(dev_priv))
-		dg1_map_plls_to_ports(encoder, crtc_state);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_map_plls_to_ports(encoder, crtc_state);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -4210,9 +4208,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (IS_DG1(dev_priv))
-		dg1_unmap_plls_to_ports(encoder);
-	else if (INTEL_GEN(dev_priv) >= 11)
+	if (!IS_DG1(dev_priv) && INTEL_GEN(dev_priv) >= 11)
 		icl_unmap_plls_to_ports(encoder);
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
@@ -5657,7 +5653,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		encoder->enable_clock = dg1_ddi_enable_clock;
+		encoder->disable_clock = dg1_ddi_disable_clock;
+	} else if (IS_CANNONLAKE(dev_priv)) {
 		encoder->enable_clock = cnl_ddi_enable_clock;
 		encoder->disable_clock = cnl_ddi_disable_clock;
 	} else if (IS_GEN9_BC(dev_priv)) {
-- 
2.26.2

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  parent reply	other threads:[~2021-02-04 18:11 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04 18:10 [Intel-gfx] [PATCH v2 00/14] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 01/14] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 02/14] drm/i915: Extract hsw_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 03/14] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 04/14] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` Ville Syrjala [this message]
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 06/14] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 07/14] drm/i915: Use intel_de_rmw() for DDI clock routing Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 08/14] drm/i915: Sprinkle a few missing locks around shared DDI clock registers Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 09/14] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 10/14] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 11/14] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 12/14] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 13/14] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 14/14] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing Ville Syrjala
2021-02-04 22:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev2) Patchwork
2021-02-04 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-04 22:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-05  5:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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