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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH v2 07/14] drm/i915: Use intel_de_rmw() for DDI clock routing
Date: Thu,  4 Feb 2021 20:10:41 +0200	[thread overview]
Message-ID: <20210204181048.24202-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210204181048.24202-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 77 +++++++++---------------
 1 file changed, 28 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d688ef231eeb..76aa7d2dba52 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3133,7 +3133,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
@@ -3146,17 +3145,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
 
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-	val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3168,8 +3162,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3180,7 +3174,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val, mask, sel;
+	u32 mask, sel;
 	i915_reg_t reg;
 
 	if (IS_ALDERLAKE_S(dev_priv)) {
@@ -3199,10 +3193,6 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
-
 	/*
 	 * Even though this register references DDIs, note that we
 	 * want to pass the PHY rather than the port (DDI).  For
@@ -3213,13 +3203,10 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	 *   Clock Select chooses the PLL for both DDIA and DDID and
 	 *   drives port A in all cases."
 	 */
-	val &= ~mask;
-	val |= sel;
-	intel_de_write(dev_priv, reg, val);
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_rmw(dev_priv, reg, mask, sel);
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3228,7 +3215,6 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 	i915_reg_t reg;
 
 	mutex_lock(&dev_priv->dpll.lock);
@@ -3238,10 +3224,10 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	else
 		reg = ICL_DPCLKA_CFGCR0;
 
-	val = intel_de_read(dev_priv, reg);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
+	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3446,25 +3432,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
 	mutex_lock(&i915->dpll.lock);
 
-	val = intel_de_read(i915, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-	intel_de_write(i915, DPCLKA_CFGCR0, val);
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
 
 	/*
 	 * "This step and the step before must be
 	 *  done with separate register writes."
 	 */
-	val = intel_de_read(i915, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	intel_de_write(i915, DPCLKA_CFGCR0, val);
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
 
 	mutex_unlock(&i915->dpll.lock);
 }
@@ -3474,8 +3457,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(i915, DPCLKA_CFGCR0,
-		       intel_de_read(i915, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+	intel_de_rmw(i915, DPCLKA_CFGCR0,
+		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3484,21 +3467,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&i915->drm, !pll))
 		return;
 
 	mutex_lock(&i915->dpll.lock);
 
-	val = intel_de_read(i915, DPLL_CTRL2);
-
-	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-	intel_de_write(i915, DPLL_CTRL2, val);
+	intel_de_rmw(i915, DPLL_CTRL2,
+		     DPLL_CTRL2_DDI_CLK_OFF(port) |
+		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
+		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
 	mutex_unlock(&i915->dpll.lock);
 }
@@ -3508,8 +3487,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(i915, DPLL_CTRL2,
-		       intel_de_read(i915, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+	intel_de_rmw(i915, DPLL_CTRL2,
+		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
 }
 
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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  parent reply	other threads:[~2021-02-04 18:11 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04 18:10 [Intel-gfx] [PATCH v2 00/14] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 01/14] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 02/14] drm/i915: Extract hsw_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 03/14] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 04/14] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 05/14] drm/i915: Convert DG1 over to .{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 06/14] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-04 18:10 ` Ville Syrjala [this message]
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 08/14] drm/i915: Sprinkle a few missing locks around shared DDI clock registers Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 09/14] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 10/14] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 11/14] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 12/14] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 13/14] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-04 18:10 ` [Intel-gfx] [PATCH v2 14/14] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing Ville Syrjala
2021-02-04 22:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev2) Patchwork
2021-02-04 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-04 22:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-05  5:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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