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From: clinton.a.taylor@intel.com
To: Intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types
Date: Thu,  4 Feb 2021 12:04:58 -0800	[thread overview]
Message-ID: <20210204200458.21875-1-clinton.a.taylor@intel.com> (raw)

From: Clint Taylor <clinton.a.taylor@intel.com>

Add DDR5 and LPDDR5 return values from punit fw.

BSPEC: 54023
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 12 +++++++++++-
 drivers/gpu/drm/i915/i915_drv.h         |  4 +++-
 drivers/gpu/drm/i915/intel_dram.c       |  6 ++++++
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ba9e713585e7..d122b9965532 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,17 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 	qi->num_points = dram_info->num_qgv_points;
 
 	if (IS_GEN(dev_priv, 12))
-		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
+		switch (dram_info->type) {
+		case INTEL_DRAM_DDR4:
+			qi->t_bl = 4;
+			break;
+		case INTEL_DRAM_DDR5:
+			qi->t_bl = 8;
+			break;
+		default:
+			qi->t_bl = 16;
+			break;
+		}
 	else if (IS_GEN(dev_priv, 11))
 		qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2fd7e5039b3..8083a50908bf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1136,7 +1136,9 @@ struct drm_i915_private {
 			INTEL_DRAM_DDR3,
 			INTEL_DRAM_DDR4,
 			INTEL_DRAM_LPDDR3,
-			INTEL_DRAM_LPDDR4
+			INTEL_DRAM_LPDDR4,
+			INTEL_DRAM_DDR5,
+			INTEL_DRAM_LPDDR5,
 		} type;
 		u8 num_qgv_points;
 	} dram_info;
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 73d256fc6830..1e53c017c30d 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -427,6 +427,12 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
 		case 0:
 			dram_info->type = INTEL_DRAM_DDR4;
 			break;
+		case 1:
+			dram_info->type = INTEL_DRAM_DDR5;
+			break;
+		case 2:
+			dram_info->type = INTEL_DRAM_LPDDR5;
+			break;
 		case 3:
 			dram_info->type = INTEL_DRAM_LPDDR4;
 			break;
-- 
2.29.2

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             reply	other threads:[~2021-02-04 20:05 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-04 20:04 clinton.a.taylor [this message]
2021-02-04 20:31 ` [Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types Souza, Jose
2021-02-04 23:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-02-05  7:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-02-05 13:25   ` Souza, Jose

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