From: Joakim Zhang <qiangqing.zhang@nxp.com>
To: mkl@pengutronix.de
Cc: linux-can@vger.kernel.org, linux-imx@nxp.com
Subject: [PATCH V3 2/3] can: flexcan: enable RX FIFO after FRZ/HALT valid
Date: Thu, 18 Feb 2021 19:00:36 +0800 [thread overview]
Message-ID: <20210218110037.16591-3-qiangqing.zhang@nxp.com> (raw)
In-Reply-To: <20210218110037.16591-1-qiangqing.zhang@nxp.com>
RX FIFO enable failed could happen when do system reboot stress test:
[ 0.303958] flexcan 5a8d0000.can: 5a8d0000.can supply xceiver not found, using dummy regulator
[ 0.304281] flexcan 5a8d0000.can (unnamed net_device) (uninitialized): Could not enable RX FIFO, unsupported core
[ 0.314640] flexcan 5a8d0000.can: registering netdev failed
[ 0.320728] flexcan 5a8e0000.can: 5a8e0000.can supply xceiver not found, using dummy regulator
[ 0.320991] flexcan 5a8e0000.can (unnamed net_device) (uninitialized): Could not enable RX FIFO, unsupported core
[ 0.331360] flexcan 5a8e0000.can: registering netdev failed
[ 0.337444] flexcan 5a8f0000.can: 5a8f0000.can supply xceiver not found, using dummy regulator
[ 0.337716] flexcan 5a8f0000.can (unnamed net_device) (uninitialized): Could not enable RX FIFO, unsupported core
[ 0.348117] flexcan 5a8f0000.can: registering netdev failed
RX FIFO should be enabled after the FRZ/HALT are valid. But the current
code enable RX FIFO and FRZ/HALT at the same time.
Fixes: e955cead03117 ("CAN: Add Flexcan CAN controller driver")
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/net/can/flexcan.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 737e594cb12c..d6a84b7e06da 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -1825,10 +1825,14 @@ static int register_flexcandev(struct net_device *dev)
if (err)
goto out_chip_disable;
- /* set freeze, halt and activate FIFO, restrict register access */
+ /* set freeze, halt */
+ err = flexcan_chip_freeze(priv);
+ if (err)
+ goto out_chip_disable;
+
+ /* activate FIFO, restrict register access */
reg = priv->read(®s->mcr);
- reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
- FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
+ reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
priv->write(reg, ®s->mcr);
/* Currently we only support newer versions of this core
--
2.17.1
next prev parent reply other threads:[~2021-02-18 11:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-18 11:00 [PATCH V3 0/3] can: flexcan: fixes for freeze mode Joakim Zhang
2021-02-18 11:00 ` [PATCH V3 1/3] can: flexcan: assert FRZ bit in flexcan_chip_freeze() Joakim Zhang
2021-02-18 11:00 ` Joakim Zhang [this message]
2021-02-18 11:00 ` [PATCH V3 3/3] can: flexcan: invoke flexcan_chip_freeze() to enter freeze mode Joakim Zhang
2021-02-18 20:36 ` [PATCH V3 0/3] can: flexcan: fixes for " Marc Kleine-Budde
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