From: Tomas Winkler <tomas.winkler@intel.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Alexander Usyskin <alexander.usyskin@intel.com>, Vitaly Lubart <vitaly.lubart@intel.com>, linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org, Tomas Winkler <tomas.winkler@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com> Subject: [RFC PATCH 05/10 v2] drm/i915/spi: implement spi access functions Date: Mon, 8 Mar 2021 08:27:43 +0200 [thread overview] Message-ID: <20210308062748.208017-6-tomas.winkler@intel.com> (raw) In-Reply-To: <20210308062748.208017-1-tomas.winkler@intel.com> Implement spi_read() spi_erase() spi_write() functions. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Co-developed-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Co-developed-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> --- V2: 1. Rebase drivers/gpu/drm/i915/spi/i915_spi.c | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/i915_spi.c b/drivers/gpu/drm/i915/spi/i915_spi.c index a1e7171d05db..df6a461d520d 100644 --- a/drivers/gpu/drm/i915/spi/i915_spi.c +++ b/drivers/gpu/drm/i915/spi/i915_spi.c @@ -9,7 +9,10 @@ #include <linux/io.h> #include <linux/device.h> #include <linux/slab.h> +#include <linux/sizes.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/platform_device.h> +#include <linux/delay.h> #include <spi/intel_spi.h> struct i915_spi { @@ -83,6 +86,33 @@ static inline u32 spi_read32(struct i915_spi *spi, u32 address) return ioread32(base + SPI_TRIGGER_REG); } +static inline u64 spi_read64(struct i915_spi *spi, u32 address) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + return readq(base + SPI_TRIGGER_REG); +} + +static void spi_write32(struct i915_spi *spi, u32 address, u32 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + iowrite32(data, base + SPI_TRIGGER_REG); +} + +static void spi_write64(struct i915_spi *spi, u32 address, u64 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + writeq(data, base + SPI_TRIGGER_REG); +} + static int spi_get_access_map(struct i915_spi *spi) { u32 flmap1; @@ -139,6 +169,113 @@ static int i915_spi_is_valid(struct i915_spi *spi) return 0; } +__maybe_unused +static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from) +{ + unsigned int i; + + for (i = 0; i < spi->nregions; i++) { + if ((spi->regions[i].offset + spi->regions[i].size - 1) > from && + spi->regions[i].offset <= from && + spi->regions[i].size != 0) + break; + } + + return i; +} + +__maybe_unused +static ssize_t spi_write(struct i915_spi *spi, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + spi_write64(spi, to + i, data); + if (spi_error(spi)) + return -EIO; + } + + if (len8 != len) { /* caller ensure that write size is at least u32 */ + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + spi_write32(spi, to + len8, data); + if (spi_error(spi)) + return -EIO; + } + + return len; +} + +__maybe_unused +static ssize_t spi_read(struct i915_spi *spi, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data = spi_read64(spi, from + i); + + if (spi_error(spi)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 = len - len8; + if (len4 >= sizeof(u32)) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i += sizeof(u32); + len4 -= sizeof(u32); + } + + if (len4 > 0) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) +{ + u64 i; + const u32 block = 0x10; + void __iomem *base = spi->base; + + for (i = 0; i < len; i += SZ_4K) { + iowrite32(from + i, base + SPI_ADDRESS_REG); + iowrite32(region << 24 | block, base + SPI_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); + } + return len; +} + static int i915_spi_init(struct i915_spi *spi, struct device *device) { int ret; -- 2.26.2 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Tomas Winkler <tomas.winkler@intel.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Jani Nikula <jani.nikula@linux.intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Alexander Usyskin <alexander.usyskin@intel.com>, intel-gfx@lists.freedesktop.org, Lucas De Marchi <lucas.demarchi@intel.com>, linux-mtd@lists.infradead.org, Tomas Winkler <tomas.winkler@intel.com>, Vitaly Lubart <vitaly.lubart@intel.com> Subject: [Intel-gfx] [RFC PATCH 05/10 v2] drm/i915/spi: implement spi access functions Date: Mon, 8 Mar 2021 08:27:43 +0200 [thread overview] Message-ID: <20210308062748.208017-6-tomas.winkler@intel.com> (raw) In-Reply-To: <20210308062748.208017-1-tomas.winkler@intel.com> Implement spi_read() spi_erase() spi_write() functions. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Co-developed-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Co-developed-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> --- V2: 1. Rebase drivers/gpu/drm/i915/spi/i915_spi.c | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/i915_spi.c b/drivers/gpu/drm/i915/spi/i915_spi.c index a1e7171d05db..df6a461d520d 100644 --- a/drivers/gpu/drm/i915/spi/i915_spi.c +++ b/drivers/gpu/drm/i915/spi/i915_spi.c @@ -9,7 +9,10 @@ #include <linux/io.h> #include <linux/device.h> #include <linux/slab.h> +#include <linux/sizes.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/platform_device.h> +#include <linux/delay.h> #include <spi/intel_spi.h> struct i915_spi { @@ -83,6 +86,33 @@ static inline u32 spi_read32(struct i915_spi *spi, u32 address) return ioread32(base + SPI_TRIGGER_REG); } +static inline u64 spi_read64(struct i915_spi *spi, u32 address) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + return readq(base + SPI_TRIGGER_REG); +} + +static void spi_write32(struct i915_spi *spi, u32 address, u32 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + iowrite32(data, base + SPI_TRIGGER_REG); +} + +static void spi_write64(struct i915_spi *spi, u32 address, u64 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + writeq(data, base + SPI_TRIGGER_REG); +} + static int spi_get_access_map(struct i915_spi *spi) { u32 flmap1; @@ -139,6 +169,113 @@ static int i915_spi_is_valid(struct i915_spi *spi) return 0; } +__maybe_unused +static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from) +{ + unsigned int i; + + for (i = 0; i < spi->nregions; i++) { + if ((spi->regions[i].offset + spi->regions[i].size - 1) > from && + spi->regions[i].offset <= from && + spi->regions[i].size != 0) + break; + } + + return i; +} + +__maybe_unused +static ssize_t spi_write(struct i915_spi *spi, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + spi_write64(spi, to + i, data); + if (spi_error(spi)) + return -EIO; + } + + if (len8 != len) { /* caller ensure that write size is at least u32 */ + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + spi_write32(spi, to + len8, data); + if (spi_error(spi)) + return -EIO; + } + + return len; +} + +__maybe_unused +static ssize_t spi_read(struct i915_spi *spi, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data = spi_read64(spi, from + i); + + if (spi_error(spi)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 = len - len8; + if (len4 >= sizeof(u32)) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i += sizeof(u32); + len4 -= sizeof(u32); + } + + if (len4 > 0) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) +{ + u64 i; + const u32 block = 0x10; + void __iomem *base = spi->base; + + for (i = 0; i < len; i += SZ_4K) { + iowrite32(from + i, base + SPI_ADDRESS_REG); + iowrite32(region << 24 | block, base + SPI_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); + } + return len; +} + static int i915_spi_init(struct i915_spi *spi, struct device *device) { int ret; -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-03-08 6:33 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-08 6:27 [RFC PATCH 00/10 v2] drm/i915/spi: discrete graphics internal spi Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 01/10 v2] drm/i915/spi: add spi device for discrete graphics Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 02/10 v2] drm/i915/spi: intel_spi_region map Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 03/10 v2] drm/i915/spi: add driver for on-die spi device Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 04/10 v2] drm/i915/spi: implement regions enumeration Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` Tomas Winkler [this message] 2021-03-08 6:27 ` [Intel-gfx] [RFC PATCH 05/10 v2] drm/i915/spi: implement spi access functions Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 06/10 v2] drm/i915/spi: spi register with mtd Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 07/10 v2] drm/i915/spi: mtd: implement access handlers Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 08/10 v2] drm/i915/spi: serialize spi access Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 09/10 v2] MAINTAINERS: add Intel i915 spi driver entry Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:27 ` [RFC PATCH 10/10 v2] mtd: use refcount to prevent corruption Tomas Winkler 2021-03-08 6:27 ` [Intel-gfx] " Tomas Winkler 2021-03-08 6:33 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/spi: discrete graphics internal spi (rev2) Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210308062748.208017-6-tomas.winkler@intel.com \ --to=tomas.winkler@intel.com \ --cc=alexander.usyskin@intel.com \ --cc=intel-gfx@lists.freedesktop.org \ --cc=jani.nikula@linux.intel.com \ --cc=joonas.lahtinen@linux.intel.com \ --cc=linux-mtd@lists.infradead.org \ --cc=lucas.demarchi@intel.com \ --cc=miquel.raynal@bootlin.com \ --cc=richard@nod.at \ --cc=rodrigo.vivi@intel.com \ --cc=vigneshr@ti.com \ --cc=vitaly.lubart@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.