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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org
Subject: [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro
Date: Thu,  6 May 2021 09:23:06 +1000	[thread overview]
Message-ID: <20210505232312.4175486-37-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h  | 10 ----------
 target/riscv/csr.c       | 12 ++++++++++--
 target/riscv/translate.c | 19 +++++++++++++++++--
 3 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d738e2fdbd..6e30b312f0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -368,16 +368,6 @@
 #define MXL_RV64            2
 #define MXL_RV128           3
 
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001
 #define SSTATUS_SIE         0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 41951a0a84..e955753441 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+    if (riscv_cpu_is_32bit(env)) {
+        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+    } else {
+        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+    }
     env->mstatus = mstatus;
 
     return RISCV_EXCP_NONE;
@@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     }
 
     /* misa.MXL writes are not supported by QEMU */
-    val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+    if (riscv_cpu_is_32bit(env)) {
+        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+    } else {
+        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+    }
 
     /* flush translation cache */
     if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 26eccc5eb1..a596f80f20 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
     return ctx->misa & ext;
 }
 
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx)  true
+#elif defined(CONFIG_USER_ONLY)
+# define is_32bit(ctx)  false
+#else
+static inline bool is_32bit(DisasContext *ctx)
+{
+    return (ctx->misa & RV32) == RV32;
+}
+#endif
+
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
+    target_ulong sd;
+
     if (ctx->mstatus_fs == MSTATUS_FS) {
         return;
     }
@@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx)
     ctx->mstatus_fs = MSTATUS_FS;
 
     tmp = tcg_temp_new();
+    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 
     if (ctx->virt_enabled) {
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
     }
     tcg_temp_free(tmp);
-- 
2.31.1



  parent reply	other threads:[~2021-05-05 23:32 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-05 23:22 [PULL v2 00/42] riscv-to-apply queue Alistair Francis
2021-05-05 23:22 ` [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-05 23:22 ` [PULL v2 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-05 23:22 ` [PULL v2 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-05 23:22 ` [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-05 23:22 ` [PULL v2 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-05 23:22 ` [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-05 23:22 ` [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-05 23:22 ` [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-05 23:22 ` [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-05 23:22 ` [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-05 23:22 ` [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-05 23:22 ` [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-05 23:22 ` [PULL v2 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-05 23:22 ` [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-05 23:22 ` [PULL v2 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-05 23:22 ` [PULL v2 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-05 23:22 ` [PULL v2 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-05 23:22 ` [PULL v2 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-05 23:22 ` [PULL v2 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-05 23:22 ` [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-05 23:22 ` [PULL v2 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-05 23:22 ` [PULL v2 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-05 23:22 ` [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-05 23:22 ` [PULL v2 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-05 23:23 ` [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-05 23:23 ` [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-05 23:23 ` [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-05 23:23 ` Alistair Francis [this message]
2021-05-05 23:23 ` [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-11  8:29 ` [PULL v2 00/42] riscv-to-apply queue Peter Maydell
2021-05-11 10:17   ` Alistair Francis

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