From: Bjorn Andersson <bjorn.andersson@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Stephen Boyd <swboyd@chromium.org>, sbillaka@codeaurora.org Cc: Tanmay Shah <tanmay@codeaurora.org>, Chandan Uddaraju <chandanu@codeaurora.org>, Abhinav Kumar <abhinavk@codeaurora.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] drm/msm/dp: Simplify the mvid/nvid calculation Date: Mon, 10 May 2021 23:20:40 -0500 [thread overview] Message-ID: <20210511042043.592802-2-bjorn.andersson@linaro.org> (raw) In-Reply-To: <20210511042043.592802-1-bjorn.andersson@linaro.org> In the search for causes to timing issues seen during implementation of eDP support for SC8180x a fair amount of time was spent concluding why the calculated mvid/nvid values where wrong. The overall conclusion is that the ratio of MVID/NVID describes, and should match, the ratio between the pixel and link clock. Downstream this calculation reads the M and N values off the pixel clock straight from DISP_CC and are then adjusted based on knowledge of how the link and vco_div (parent of the pixel clock) are derrived from the common VCO. While upstreaming, and then extracting the PHY driver, the resulting function performs the following steps: 1) Adjust the passed link rate based on the VCO divider used in the PHY driver, and multiply this by 10 based on the link rate divider. 2) Pick reasonable choices of M and N, by calculating the ratio between this new clock and the pixel clock. 3) Subtract M from N and flip the bits, to match the encoding of the N register in DISP_CC. 4) Flip the bits of N and add M, to get the value of N back. 5) Multiply M with 5, per the documentation. 6) Scale the values such that N is close to 0x8000 (or larger) 7) Multply M with 2 or 3 depending on the link rate of HBR2 or HBR3. Presumably step 3) was added to provide step 4) with expected input, so the two cancel each other out. The factor of 10 from step 1) goes into the denominator and is partially cancelled by the 5 in the numerator in step 5), resulting in step 7) simply cancelling out step 1). Left is the code that finds the ratio between the two arguments, scaled to keep the denominator close to or larger than 0x8000. And this is our mvid/nvid pair. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 41 +++++------------------------ 1 file changed, 6 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index b1a9b1b98f5f..2eb37ee48e42 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -415,39 +415,16 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid) { - u32 pixel_m, pixel_n; - u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; - u32 const link_rate_hbr2 = 540000; - u32 const link_rate_hbr3 = 810000; - unsigned long den, num; - + unsigned long mvid, nvid; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - if (rate == link_rate_hbr3) - pixel_div = 6; - else if (rate == 1620000 || rate == 270000) - pixel_div = 2; - else if (rate == link_rate_hbr2) - pixel_div = 4; - else - DRM_ERROR("Invalid pixel mux divider\n"); - - dispcc_input_rate = (rate * 10) / pixel_div; - - rational_best_approximation(dispcc_input_rate, stream_rate_khz, - (unsigned long)(1 << 16) - 1, - (unsigned long)(1 << 16) - 1, &den, &num); - - den = ~(den - num); - den = den & 0xFFFF; - pixel_m = num; - pixel_n = den; - - mvid = (pixel_m & 0xFFFF) * 5; - nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + rational_best_approximation(stream_rate_khz, rate, + (1 << 16) - 1, (1 << 16) - 1, + &mvid, &nvid); + /* Adjust values so that nvid is close to DP_LINK_CONSTANT_N_VALUE */ if (nvid < nvid_fixed) { u32 temp; @@ -456,13 +433,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, nvid = temp; } - if (link_rate_hbr2 == rate) - nvid *= 2; - - if (link_rate_hbr3 == rate) - nvid *= 3; - - DRM_DEBUG_DP("mvid=0x%x, nvid=0x%x\n", mvid, nvid); + DRM_DEBUG_DP("mvid=0x%lx, nvid=0x%lx\n", mvid, nvid); dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <bjorn.andersson@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>, Stephen Boyd <swboyd@chromium.org>, sbillaka@codeaurora.org Cc: Tanmay Shah <tanmay@codeaurora.org>, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abhinav Kumar <abhinavk@codeaurora.org>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, freedreno@lists.freedesktop.org, Chandan Uddaraju <chandanu@codeaurora.org> Subject: [PATCH 1/4] drm/msm/dp: Simplify the mvid/nvid calculation Date: Mon, 10 May 2021 23:20:40 -0500 [thread overview] Message-ID: <20210511042043.592802-2-bjorn.andersson@linaro.org> (raw) In-Reply-To: <20210511042043.592802-1-bjorn.andersson@linaro.org> In the search for causes to timing issues seen during implementation of eDP support for SC8180x a fair amount of time was spent concluding why the calculated mvid/nvid values where wrong. The overall conclusion is that the ratio of MVID/NVID describes, and should match, the ratio between the pixel and link clock. Downstream this calculation reads the M and N values off the pixel clock straight from DISP_CC and are then adjusted based on knowledge of how the link and vco_div (parent of the pixel clock) are derrived from the common VCO. While upstreaming, and then extracting the PHY driver, the resulting function performs the following steps: 1) Adjust the passed link rate based on the VCO divider used in the PHY driver, and multiply this by 10 based on the link rate divider. 2) Pick reasonable choices of M and N, by calculating the ratio between this new clock and the pixel clock. 3) Subtract M from N and flip the bits, to match the encoding of the N register in DISP_CC. 4) Flip the bits of N and add M, to get the value of N back. 5) Multiply M with 5, per the documentation. 6) Scale the values such that N is close to 0x8000 (or larger) 7) Multply M with 2 or 3 depending on the link rate of HBR2 or HBR3. Presumably step 3) was added to provide step 4) with expected input, so the two cancel each other out. The factor of 10 from step 1) goes into the denominator and is partially cancelled by the 5 in the numerator in step 5), resulting in step 7) simply cancelling out step 1). Left is the code that finds the ratio between the two arguments, scaled to keep the denominator close to or larger than 0x8000. And this is our mvid/nvid pair. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 41 +++++------------------------ 1 file changed, 6 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index b1a9b1b98f5f..2eb37ee48e42 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -415,39 +415,16 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid) { - u32 pixel_m, pixel_n; - u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE; - u32 const link_rate_hbr2 = 540000; - u32 const link_rate_hbr3 = 810000; - unsigned long den, num; - + unsigned long mvid, nvid; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - if (rate == link_rate_hbr3) - pixel_div = 6; - else if (rate == 1620000 || rate == 270000) - pixel_div = 2; - else if (rate == link_rate_hbr2) - pixel_div = 4; - else - DRM_ERROR("Invalid pixel mux divider\n"); - - dispcc_input_rate = (rate * 10) / pixel_div; - - rational_best_approximation(dispcc_input_rate, stream_rate_khz, - (unsigned long)(1 << 16) - 1, - (unsigned long)(1 << 16) - 1, &den, &num); - - den = ~(den - num); - den = den & 0xFFFF; - pixel_m = num; - pixel_n = den; - - mvid = (pixel_m & 0xFFFF) * 5; - nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); + rational_best_approximation(stream_rate_khz, rate, + (1 << 16) - 1, (1 << 16) - 1, + &mvid, &nvid); + /* Adjust values so that nvid is close to DP_LINK_CONSTANT_N_VALUE */ if (nvid < nvid_fixed) { u32 temp; @@ -456,13 +433,7 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, nvid = temp; } - if (link_rate_hbr2 == rate) - nvid *= 2; - - if (link_rate_hbr3 == rate) - nvid *= 3; - - DRM_DEBUG_DP("mvid=0x%x, nvid=0x%x\n", mvid, nvid); + DRM_DEBUG_DP("mvid=0x%lx, nvid=0x%lx\n", mvid, nvid); dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); -- 2.29.2
next prev parent reply other threads:[~2021-05-11 4:20 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-11 4:20 [PATCH 0/4] drm/msm/dp: Add support for SC8180x eDP controller Bjorn Andersson 2021-05-11 4:20 ` Bjorn Andersson 2021-05-11 4:20 ` Bjorn Andersson [this message] 2021-05-11 4:20 ` [PATCH 1/4] drm/msm/dp: Simplify the mvid/nvid calculation Bjorn Andersson 2021-05-28 23:11 ` [Freedreno] " abhinavk 2021-05-28 23:11 ` abhinavk 2021-06-08 20:13 ` Bjorn Andersson 2021-06-08 20:13 ` Bjorn Andersson 2021-06-09 0:08 ` abhinavk 2021-06-09 0:08 ` abhinavk 2021-05-11 4:20 ` [PATCH 2/4] drm/msm/dp: Store each subblock in the io region Bjorn Andersson 2021-05-11 4:20 ` Bjorn Andersson 2021-05-28 23:14 ` [Freedreno] " abhinavk 2021-05-28 23:14 ` abhinavk 2021-05-11 4:20 ` [PATCH 3/4] drm/msm/dp: Initialize the INTF_CONFIG register Bjorn Andersson 2021-05-11 4:20 ` Bjorn Andersson 2021-05-28 23:28 ` [Freedreno] " abhinavk 2021-05-28 23:28 ` abhinavk 2021-05-11 4:20 ` [PATCH 4/4] drm/msm/dp: Add support for SC8180x eDP Bjorn Andersson 2021-05-11 4:20 ` Bjorn Andersson 2021-05-28 23:40 ` [Freedreno] " abhinavk 2021-05-28 23:40 ` abhinavk 2021-05-29 17:09 ` Bjorn Andersson 2021-05-29 17:09 ` Bjorn Andersson 2021-06-04 21:56 ` Stephen Boyd 2021-06-04 21:56 ` Stephen Boyd 2021-05-19 3:41 ` [Freedreno] [PATCH 0/4] drm/msm/dp: Add support for SC8180x eDP controller abhinavk 2021-05-19 3:41 ` abhinavk 2021-05-19 14:51 ` Bjorn Andersson 2021-05-19 14:51 ` Bjorn Andersson 2021-05-28 22:37 ` abhinavk 2021-05-28 22:37 ` abhinavk
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