From: Ralf Schlatterbeck <rsc@runtux.com> To: Andre Przywara <andre.przywara@arm.com> Cc: Mark Brown <broonie@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Mirko Vogt <mirko-dev|linux@nanl.de> Subject: [PATCH 1/1] spi-sun6i: Fix chipselect/clock bug Date: Fri, 21 May 2021 22:19:13 +0200 [thread overview] Message-ID: <20210521201913.2gapcmrzynxekro7@runtux.com> (raw) In-Reply-To: <20210521173011.1c602682@slackpad.fritz.box> From: Mirko Vogt <mirko-dev|linux@nanl.de> The current sun6i SPI implementation initializes the transfer too early, resulting in SCK going high before the transfer. When using an additional (gpio) chipselect with sun6i, the chipselect is asserted at a time when clock is high, making the SPI transfer fail. This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer function, hence, right before the transfer starts, mitigates that problem. Signed-off-by: Mirko Vogt <mirko-dev|linux@nanl.de> Signed-off-by: Ralf Schlatterbeck <rsc@runtux.com> --- Updated patch with suggested improvements by Andre Przywara For oscilloscope screenshots with/without the patch, see my blog post https://blog.runtux.com/posts/2019/04/18/ or the discussion in the armbian forum at https://forum.armbian.com/topic/4330-spi-gpio-chip-select-support/ (my logo there is a penguin). drivers/spi/spi-sun6i.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index cc8401980125..23ad052528db 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -379,6 +379,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, } sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); + /* Finally enable the bus - doing so before might raise SCK to HIGH */ + reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); + reg |= SUN6I_GBL_CTL_BUS_ENABLE; + sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); /* Setup the transfer now... */ if (sspi->tx_buf) @@ -504,7 +508,7 @@ static int sun6i_spi_runtime_resume(struct device *dev) } sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, - SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); + SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); return 0; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ralf Schlatterbeck <rsc@runtux.com> To: Andre Przywara <andre.przywara@arm.com> Cc: Mark Brown <broonie@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Mirko Vogt <mirko-dev|linux@nanl.de> Subject: [PATCH 1/1] spi-sun6i: Fix chipselect/clock bug Date: Fri, 21 May 2021 22:19:13 +0200 [thread overview] Message-ID: <20210521201913.2gapcmrzynxekro7@runtux.com> (raw) In-Reply-To: <20210521173011.1c602682@slackpad.fritz.box> From: Mirko Vogt <mirko-dev|linux@nanl.de> The current sun6i SPI implementation initializes the transfer too early, resulting in SCK going high before the transfer. When using an additional (gpio) chipselect with sun6i, the chipselect is asserted at a time when clock is high, making the SPI transfer fail. This is due to SUN6I_GBL_CTL_BUS_ENABLE being written into SUN6I_GBL_CTL_REG at an early stage. Moving that to the transfer function, hence, right before the transfer starts, mitigates that problem. Signed-off-by: Mirko Vogt <mirko-dev|linux@nanl.de> Signed-off-by: Ralf Schlatterbeck <rsc@runtux.com> --- Updated patch with suggested improvements by Andre Przywara For oscilloscope screenshots with/without the patch, see my blog post https://blog.runtux.com/posts/2019/04/18/ or the discussion in the armbian forum at https://forum.armbian.com/topic/4330-spi-gpio-chip-select-support/ (my logo there is a penguin). drivers/spi/spi-sun6i.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index cc8401980125..23ad052528db 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -379,6 +379,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, } sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); + /* Finally enable the bus - doing so before might raise SCK to HIGH */ + reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); + reg |= SUN6I_GBL_CTL_BUS_ENABLE; + sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); /* Setup the transfer now... */ if (sspi->tx_buf) @@ -504,7 +508,7 @@ static int sun6i_spi_runtime_resume(struct device *dev) } sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, - SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); + SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); return 0; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-21 20:19 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-20 10:06 [PATCH 1/1] spi-sun6i: Fix chipselect/clock bug Ralf Schlatterbeck 2021-05-20 10:06 ` Ralf Schlatterbeck 2021-05-21 16:30 ` Andre Przywara 2021-05-21 16:30 ` Andre Przywara 2021-05-21 20:16 ` Ralf Schlatterbeck 2021-05-21 20:16 ` Ralf Schlatterbeck 2021-05-21 20:19 ` Ralf Schlatterbeck [this message] 2021-05-21 20:19 ` Ralf Schlatterbeck 2021-05-24 12:33 ` Andre Przywara 2021-05-24 12:33 ` Andre Przywara 2021-05-24 16:24 ` Ralf Schlatterbeck 2021-05-24 16:24 ` Ralf Schlatterbeck 2021-05-25 14:35 ` Mark Brown 2021-05-25 14:35 ` Mark Brown 2021-05-27 11:39 ` Ralf Schlatterbeck 2021-05-27 11:39 ` Ralf Schlatterbeck 2021-06-05 14:06 ` Mirko Vogt 2021-06-05 14:06 ` Mirko Vogt 2021-06-14 14:47 ` Ralf Schlatterbeck 2021-06-14 14:47 ` Ralf Schlatterbeck
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