From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-pci@vger.kernel.org
Cc: "Martin Mareš" <mj@ucw.cz>,
"Dan Williams" <dan.j.williams@intel.com>,
"Ben Widawsky" <ben.widawsky@intel.com>
Subject: [PATCH 8/9] cxl: Add DVSEC Register Locator
Date: Fri, 4 Jun 2021 12:05:40 -0700 [thread overview]
Message-ID: <20210604190541.175602-9-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
| 8 ++++++++
ls-ecaps.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
--git a/lib/header.h b/lib/header.h
index 8141e13..b77a611 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1120,6 +1120,14 @@
#define PCI_CXL_PORT_ALT_BUS_BASE 0xe
#define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf
+/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */
+#define PCI_CXL_RL_BASE0_LO 0x0c
+#define PCI_CXL_RL_BASE0_HI 0x10
+#define PCI_CXL_RL_BASE1_LO 0x14
+#define PCI_CXL_RL_BASE1_HI 0x18
+#define PCI_CXL_RL_BASE2_LO 0x1c
+#define PCI_CXL_RL_BASE2_HI 0x20
+
/* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index b11d5a9..a0ef83d 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -800,9 +800,46 @@ dvsec_cxl_port(uint8_t* data, int rev)
printf("\t\tAlternateBus: %02x-%02x\n", b1, b2);
}
+static const char *id[] = {
+ "empty",
+ "component registers",
+ "BAR virtualization",
+ "CXL device registers"};
+
+static inline void
+dvsec_decode_block(uint32_t lo, uint32_t hi, char which)
+{
+ u64 base_hi = hi, base_lo;
+ u8 bir, block_id;
+
+ bir = BITS(lo, 0, 3);
+ block_id = BITS(lo, 8, 8);
+ base_lo = BITS(lo, 16, 16);
+
+ if (!block_id)
+ return;
+
+ printf("\t\tBlock%c\tBIR: bar%d\tID: %s\n", which, bir, id[block_id]);
+ printf("\t\t\tRegisterOffset: %016" PCI_U64_FMT_X "\n", (base_hi << 32ULL) | base_lo << 16);
+}
+
+static void
+dvsec_cxl_register_locator(uint8_t* data, int len, int rev)
+{
+ int i, j;
+
+ if (rev != 0)
+ return;
+
+ for (i = 0xc, j = 1; i < len; i += 8, j++) {
+ dvsec_decode_block(*(u32 *)(data + i), *(u32 *)(data + i + 4), j + 0x31);
+ }
+}
+
static void
cap_dvsec_cxl(struct device *d, int id, int where)
{
+ u16 len;
u8 rev;
printf(": CXL\n");
@@ -824,6 +861,13 @@ cap_dvsec_cxl(struct device *d, int id, int where)
dvsec_cxl_port(d->config + where, rev);
break;
+ case 8:
+ len = BITS(get_conf_word(d, where + 0x6), 4, 12);
+ if (!config_fetch(d, where, len))
+ return;
+
+ dvsec_cxl_register_locator(d->config + where, len, rev);
+ break;
default:
break;
}
--
2.31.1
next prev parent reply other threads:[~2021-06-04 19:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 19:05 [PATCH 0/9] Add CXL 2.0 DVSEC Decoding Ben Widawsky
2021-06-04 19:05 ` [PATCH 1/9] cxl: Rename variable to match other code Ben Widawsky
2021-06-04 19:05 ` [PATCH 2/9] cxl: Make id check more explicit Ben Widawsky
2021-06-04 19:05 ` [PATCH 3/9] cxl: Collect all DVSEC Device fields Ben Widawsky
2021-06-04 19:05 ` [PATCH 4/9] cxl: Rework caps to new function Ben Widawsky
2021-06-04 19:05 ` [PATCH 5/9] cxl: Rename caps to be device caps Ben Widawsky
2021-06-04 19:05 ` [PATCH 6/9] cxl: Implement more device DVSEC decoding Ben Widawsky
2021-06-07 16:10 ` [PATCH v2 " Ben Widawsky
2021-06-04 19:05 ` [PATCH 7/9] cxl: Add support for DVSEC port cap Ben Widawsky
2021-06-04 19:05 ` Ben Widawsky [this message]
2021-06-04 19:05 ` [PATCH 9/9] cxl: Add placeholder for undecoded DVSECs Ben Widawsky
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210604190541.175602-9-ben.widawsky@intel.com \
--to=ben.widawsky@intel.com \
--cc=dan.j.williams@intel.com \
--cc=linux-pci@vger.kernel.org \
--cc=mj@ucw.cz \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.