From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions Date: Thu, 24 Jun 2021 18:54:59 +0800 [thread overview] Message-ID: <20210624105521.3964-16-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Always contain a 32x32 multiplification and the most significant word can be used as the result, or an operand for an add or subtract operation with rounding or saturation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvp.c.inc | 44 ++++++++++ target/riscv/packed_helper.c | 109 ++++++++++++++++++++++++ 4 files changed, 171 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9872f5efbd..600e8dee44 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1271,3 +1271,12 @@ DEF_HELPER_3(pkbb16, tl, env, tl, tl) DEF_HELPER_3(pkbt16, tl, env, tl, tl) DEF_HELPER_3(pktt16, tl, env, tl, tl) DEF_HELPER_3(pktb16, tl, env, tl, tl) + +DEF_HELPER_3(smmul, tl, env, tl, tl) +DEF_HELPER_3(smmul_u, tl, env, tl, tl) +DEF_HELPER_4(kmmac, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmac_u, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmsb, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmsb_u, tl, env, tl, tl, tl) +DEF_HELPER_3(kwmmul, tl, env, tl, tl) +DEF_HELPER_3(kwmmul_u, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0b6830c76e..0484de140b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -874,3 +874,12 @@ pkbb16 0000111 ..... ..... 001 ..... 1110111 @r pkbt16 0001111 ..... ..... 001 ..... 1110111 @r pktt16 0010111 ..... ..... 001 ..... 1110111 @r pktb16 0011111 ..... ..... 001 ..... 1110111 @r + +smmul 0100000 ..... ..... 001 ..... 1110111 @r +smmul_u 0101000 ..... ..... 001 ..... 1110111 @r +kmmac 0110000 ..... ..... 001 ..... 1110111 @r +kmmac_u 0111000 ..... ..... 001 ..... 1110111 @r +kmmsb 0100001 ..... ..... 001 ..... 1110111 @r +kmmsb_u 0101001 ..... ..... 001 ..... 1110111 @r +kwmmul 0110001 ..... ..... 001 ..... 1110111 @r +kwmmul_u 0111001 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index b5bd8b1406..073558b950 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -369,3 +369,47 @@ GEN_RVP_R_OOL(pkbb16); GEN_RVP_R_OOL(pkbt16); GEN_RVP_R_OOL(pktt16); GEN_RVP_R_OOL(pktb16); + +/* Most Significant Word “32x32” Multiply & Add Instructions */ +GEN_RVP_R_OOL(smmul); +GEN_RVP_R_OOL(smmul_u); + +/* Function to accumulate destination register */ +static inline bool r_acc_ool(DisasContext *ctx, arg_r *a, + void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv, TCGv)) +{ + TCGv src1, src2, src3, dst; + if (!has_ext(ctx, RVP)) { + return false; + } + + src1 = tcg_temp_new(); + src2 = tcg_temp_new(); + src3 = tcg_temp_new(); + dst = tcg_temp_new(); + + gen_get_gpr(src1, a->rs1); + gen_get_gpr(src2, a->rs2); + gen_get_gpr(src3, a->rd); + fn(dst, cpu_env, src1, src2, src3); + gen_set_gpr(a->rd, dst); + + tcg_temp_free(src1); + tcg_temp_free(src2); + tcg_temp_free(src3); + tcg_temp_free(dst); + return true; +} + +#define GEN_RVP_R_ACC_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + return r_acc_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP_R_ACC_OOL(kmmac); +GEN_RVP_R_ACC_OOL(kmmac_u); +GEN_RVP_R_ACC_OOL(kmmsb); +GEN_RVP_R_ACC_OOL(kmmsb_u); +GEN_RVP_R_OOL(kwmmul); +GEN_RVP_R_OOL(kwmmul_u); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index f6cea654b2..465cb5a3b3 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1359,3 +1359,112 @@ static inline void do_pktb16(CPURISCVState *env, void *vd, void *va, } RVPR(pktb16, 2, 2); + +/* Most Significant Word “32x32” Multiply & Add Instructions */ +static inline void do_smmul(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + d[i] = (int64_t)a[i] * b[i] >> 32; +} + +RVPR(smmul, 1, 4); + +static inline void do_smmul_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + d[i] = ((int64_t)a[i] * b[i] + (uint32_t)INT32_MIN) >> 32; +} + +RVPR(smmul_u, 1, 4); + +typedef void PackedFn4i(CPURISCVState *, void *, void *, + void *, void *, uint8_t); + +static inline target_ulong +rvpr_acc(CPURISCVState *env, target_ulong a, + target_ulong b, target_ulong c, + uint8_t step, uint8_t size, PackedFn4i *fn) +{ + int i, passes = sizeof(target_ulong) / size; + target_ulong result = 0; + + for (i = 0; i < passes; i += step) { + fn(env, &result, &a, &b, &c, i); + } + return result; +} + +#define RVPR_ACC(NAME, STEP, SIZE) \ +target_ulong HELPER(NAME)(CPURISCVState *env, target_ulong a, \ + target_ulong b, target_ulong c) \ +{ \ + return rvpr_acc(env, a, b, c, STEP, SIZE, (PackedFn4i *)do_##NAME);\ +} + +static inline void do_kmmac(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i]) >> 32, c[i]); +} + +RVPR_ACC(kmmac, 1, 4); + +static inline void do_kmmac_u(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i] + + (uint32_t)INT32_MIN) >> 32, c[i]); +} + +RVPR_ACC(kmmac_u, 1, 4); + +static inline void do_kmmsb(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = ssub32(env, 0, c[i], (int64_t)a[i] * b[i] >> 32); +} + +RVPR_ACC(kmmsb, 1, 4); + +static inline void do_kmmsb_u(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = ssub32(env, 0, c[i], ((int64_t)a[i] * b[i] + + (uint32_t)INT32_MIN) >> 32); +} + +RVPR_ACC(kmmsb_u, 1, 4); + +static inline void do_kwmmul(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + if (a[i] == INT32_MIN && b[i] == INT32_MIN) { + env->vxsat = 0x1; + d[i] = INT32_MAX; + } else { + d[i] = (int64_t)a[i] * b[i] >> 31; + } +} + +RVPR(kwmmul, 1, 4); + +static inline void do_kwmmul_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + if (a[i] == INT32_MIN && b[i] == INT32_MIN) { + env->vxsat = 0x1; + d[i] = INT32_MAX; + } else { + d[i] = ((int64_t)a[i] * b[i] + (1ull << 30)) >> 31; + } +} + +RVPR(kwmmul_u, 1, 4); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions Date: Thu, 24 Jun 2021 18:54:59 +0800 [thread overview] Message-ID: <20210624105521.3964-16-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Always contain a 32x32 multiplification and the most significant word can be used as the result, or an operand for an add or subtract operation with rounding or saturation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 9 ++ target/riscv/insn_trans/trans_rvp.c.inc | 44 ++++++++++ target/riscv/packed_helper.c | 109 ++++++++++++++++++++++++ 4 files changed, 171 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9872f5efbd..600e8dee44 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1271,3 +1271,12 @@ DEF_HELPER_3(pkbb16, tl, env, tl, tl) DEF_HELPER_3(pkbt16, tl, env, tl, tl) DEF_HELPER_3(pktt16, tl, env, tl, tl) DEF_HELPER_3(pktb16, tl, env, tl, tl) + +DEF_HELPER_3(smmul, tl, env, tl, tl) +DEF_HELPER_3(smmul_u, tl, env, tl, tl) +DEF_HELPER_4(kmmac, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmac_u, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmsb, tl, env, tl, tl, tl) +DEF_HELPER_4(kmmsb_u, tl, env, tl, tl, tl) +DEF_HELPER_3(kwmmul, tl, env, tl, tl) +DEF_HELPER_3(kwmmul_u, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0b6830c76e..0484de140b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -874,3 +874,12 @@ pkbb16 0000111 ..... ..... 001 ..... 1110111 @r pkbt16 0001111 ..... ..... 001 ..... 1110111 @r pktt16 0010111 ..... ..... 001 ..... 1110111 @r pktb16 0011111 ..... ..... 001 ..... 1110111 @r + +smmul 0100000 ..... ..... 001 ..... 1110111 @r +smmul_u 0101000 ..... ..... 001 ..... 1110111 @r +kmmac 0110000 ..... ..... 001 ..... 1110111 @r +kmmac_u 0111000 ..... ..... 001 ..... 1110111 @r +kmmsb 0100001 ..... ..... 001 ..... 1110111 @r +kmmsb_u 0101001 ..... ..... 001 ..... 1110111 @r +kwmmul 0110001 ..... ..... 001 ..... 1110111 @r +kwmmul_u 0111001 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index b5bd8b1406..073558b950 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -369,3 +369,47 @@ GEN_RVP_R_OOL(pkbb16); GEN_RVP_R_OOL(pkbt16); GEN_RVP_R_OOL(pktt16); GEN_RVP_R_OOL(pktb16); + +/* Most Significant Word “32x32” Multiply & Add Instructions */ +GEN_RVP_R_OOL(smmul); +GEN_RVP_R_OOL(smmul_u); + +/* Function to accumulate destination register */ +static inline bool r_acc_ool(DisasContext *ctx, arg_r *a, + void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv, TCGv)) +{ + TCGv src1, src2, src3, dst; + if (!has_ext(ctx, RVP)) { + return false; + } + + src1 = tcg_temp_new(); + src2 = tcg_temp_new(); + src3 = tcg_temp_new(); + dst = tcg_temp_new(); + + gen_get_gpr(src1, a->rs1); + gen_get_gpr(src2, a->rs2); + gen_get_gpr(src3, a->rd); + fn(dst, cpu_env, src1, src2, src3); + gen_set_gpr(a->rd, dst); + + tcg_temp_free(src1); + tcg_temp_free(src2); + tcg_temp_free(src3); + tcg_temp_free(dst); + return true; +} + +#define GEN_RVP_R_ACC_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + return r_acc_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP_R_ACC_OOL(kmmac); +GEN_RVP_R_ACC_OOL(kmmac_u); +GEN_RVP_R_ACC_OOL(kmmsb); +GEN_RVP_R_ACC_OOL(kmmsb_u); +GEN_RVP_R_OOL(kwmmul); +GEN_RVP_R_OOL(kwmmul_u); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index f6cea654b2..465cb5a3b3 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1359,3 +1359,112 @@ static inline void do_pktb16(CPURISCVState *env, void *vd, void *va, } RVPR(pktb16, 2, 2); + +/* Most Significant Word “32x32” Multiply & Add Instructions */ +static inline void do_smmul(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + d[i] = (int64_t)a[i] * b[i] >> 32; +} + +RVPR(smmul, 1, 4); + +static inline void do_smmul_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + d[i] = ((int64_t)a[i] * b[i] + (uint32_t)INT32_MIN) >> 32; +} + +RVPR(smmul_u, 1, 4); + +typedef void PackedFn4i(CPURISCVState *, void *, void *, + void *, void *, uint8_t); + +static inline target_ulong +rvpr_acc(CPURISCVState *env, target_ulong a, + target_ulong b, target_ulong c, + uint8_t step, uint8_t size, PackedFn4i *fn) +{ + int i, passes = sizeof(target_ulong) / size; + target_ulong result = 0; + + for (i = 0; i < passes; i += step) { + fn(env, &result, &a, &b, &c, i); + } + return result; +} + +#define RVPR_ACC(NAME, STEP, SIZE) \ +target_ulong HELPER(NAME)(CPURISCVState *env, target_ulong a, \ + target_ulong b, target_ulong c) \ +{ \ + return rvpr_acc(env, a, b, c, STEP, SIZE, (PackedFn4i *)do_##NAME);\ +} + +static inline void do_kmmac(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i]) >> 32, c[i]); +} + +RVPR_ACC(kmmac, 1, 4); + +static inline void do_kmmac_u(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i] + + (uint32_t)INT32_MIN) >> 32, c[i]); +} + +RVPR_ACC(kmmac_u, 1, 4); + +static inline void do_kmmsb(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = ssub32(env, 0, c[i], (int64_t)a[i] * b[i] >> 32); +} + +RVPR_ACC(kmmsb, 1, 4); + +static inline void do_kmmsb_u(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb, *c = vc; + d[i] = ssub32(env, 0, c[i], ((int64_t)a[i] * b[i] + + (uint32_t)INT32_MIN) >> 32); +} + +RVPR_ACC(kmmsb_u, 1, 4); + +static inline void do_kwmmul(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + if (a[i] == INT32_MIN && b[i] == INT32_MIN) { + env->vxsat = 0x1; + d[i] = INT32_MAX; + } else { + d[i] = (int64_t)a[i] * b[i] >> 31; + } +} + +RVPR(kwmmul, 1, 4); + +static inline void do_kwmmul_u(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + if (a[i] == INT32_MIN && b[i] == INT32_MIN) { + env->vxsat = 0x1; + d[i] = INT32_MAX; + } else { + d[i] = ((int64_t)a[i] * b[i] + (1ull << 30)) >> 31; + } +} + +RVPR(kwmmul_u, 1, 4); -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:18 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei [this message] 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
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