From: "Pali Rohár" <pali@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh@kernel.org>, Gregory Clement <gregory.clement@bootlin.com> Cc: "Marek Behún" <kabel@kernel.org>, "Remi Pommarel" <repk@triplefau.lt>, Xogium <contact@xogium.me>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, "Nadav Haklai" <nadavh@marvell.com>, "Kostya Porotchkin" <kostap@marvell.com>, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 4/5] PCI: aardvark: Implement workaround for the readback value of VEND_ID Date: Fri, 25 Jun 2021 00:26:20 +0200 [thread overview] Message-ID: <20210624222621.4776-5-pali@kernel.org> (raw) In-Reply-To: <20210624222621.4776-1-pali@kernel.org> Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in aardvark driver for both PCI vendor id and PCI subsystem vendor id. This change affects and fixes PCI vendor id of emulated PCIe root bridge. After this change emulated PCIe root bridge has correct vendor id. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 397431d641f6..9ff68abd8d1e 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -166,6 +166,7 @@ #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 #define RC_BAR_CONFIG 0x300 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -417,6 +418,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; + advk_writel(pcie, reg, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: "Pali Rohár" <pali@kernel.org> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh@kernel.org>, Gregory Clement <gregory.clement@bootlin.com> Cc: "Marek Behún" <kabel@kernel.org>, "Remi Pommarel" <repk@triplefau.lt>, Xogium <contact@xogium.me>, "Tomasz Maciej Nowak" <tmn505@gmail.com>, "Nadav Haklai" <nadavh@marvell.com>, "Kostya Porotchkin" <kostap@marvell.com>, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 4/5] PCI: aardvark: Implement workaround for the readback value of VEND_ID Date: Fri, 25 Jun 2021 00:26:20 +0200 [thread overview] Message-ID: <20210624222621.4776-5-pali@kernel.org> (raw) In-Reply-To: <20210624222621.4776-1-pali@kernel.org> Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in aardvark driver for both PCI vendor id and PCI subsystem vendor id. This change affects and fixes PCI vendor id of emulated PCIe root bridge. After this change emulated PCIe root bridge has correct vendor id. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Cc: stable@vger.kernel.org --- drivers/pci/controller/pci-aardvark.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index 397431d641f6..9ff68abd8d1e 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -166,6 +166,7 @@ #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 #define RC_BAR_CONFIG 0x300 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -417,6 +418,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; + advk_writel(pcie, reg, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-24 22:27 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 22:26 [RESEND PATCH 0/5] PCI: aardvark: Initialization fixes Pali Rohár 2021-06-24 22:26 ` Pali Rohár 2021-06-24 22:26 ` [RESEND PATCH 1/5] PCI: aardvark: Fix link training Pali Rohár 2021-06-24 22:26 ` Pali Rohár 2021-06-24 22:26 ` [RESEND PATCH 2/5] PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros Pali Rohár 2021-06-24 22:26 ` Pali Rohár 2021-08-13 15:46 ` Lorenzo Pieralisi 2021-08-13 15:46 ` Lorenzo Pieralisi 2021-08-24 19:00 ` Bjorn Helgaas 2021-08-24 19:00 ` Bjorn Helgaas 2021-06-24 22:26 ` [RESEND PATCH 3/5] PCI: aardvark: Fix PCIe Max Payload Size setting Pali Rohár 2021-06-24 22:26 ` Pali Rohár 2021-06-24 22:26 ` Pali Rohár [this message] 2021-06-24 22:26 ` [RESEND PATCH 4/5] PCI: aardvark: Implement workaround for the readback value of VEND_ID Pali Rohár 2021-06-24 22:26 ` [RESEND PATCH 5/5] PCI: aardvark: Implement workaround for PCIe Completion Timeout Pali Rohár 2021-06-24 22:26 ` Pali Rohár 2021-08-25 19:59 ` Pali Rohár 2021-08-25 19:59 ` Pali Rohár 2021-09-08 19:42 ` Pali Rohár 2021-09-08 19:42 ` Pali Rohár 2021-06-25 12:52 ` [RESEND PATCH 0/5] PCI: aardvark: Initialization fixes Lorenzo Pieralisi 2021-06-25 12:52 ` Lorenzo Pieralisi
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210624222621.4776-5-pali@kernel.org \ --to=pali@kernel.org \ --cc=bhelgaas@google.com \ --cc=contact@xogium.me \ --cc=gregory.clement@bootlin.com \ --cc=kabel@kernel.org \ --cc=kostap@marvell.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=nadavh@marvell.com \ --cc=repk@triplefau.lt \ --cc=robh@kernel.org \ --cc=thomas.petazzoni@bootlin.com \ --cc=tmn505@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.