From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi <lucas.demarchi@intel.com>, James Ausmus <james.ausmus@intel.com>, dri-devel@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com> Subject: [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Date: Thu, 1 Jul 2021 13:23:34 -0700 [thread overview] Message-ID: <20210701202427.1547543-1-matthew.d.roper@intel.com> (raw) This series provides some of the initial enablement patches for two upcoming discrete GPUs: * XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP * DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP Both platforms will need additional enablement patches beyond what's present in this series before they're truly usable, including various LMEM and GuC work that's already happening separately. The new features/functionality that these platforms bring (such as multi-tile support, dedicated compute engines, etc.) may be referenced in passing in some of these patches but will be fully enabled in future series. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Akeem G Abodunrin (1): drm/i915/dg2: Add new LRI reg offsets Animesh Manna (1): drm/i915/dg2: Update to bigjoiner path Ankit Nautiyal (1): drm/i915/dg2: Configure PCON in DP pre-enable path Anusha Srivatsa (2): drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable drm/i915/display/dsc: Set BPP in the kernel Daniele Ceraolo Spurio (1): drm/i915/xehp: handle new steering options Gwan-gyeong Mun (1): drm/i915/dg2: Update lane disable power state during PSR John Harrison (4): drm/i915/selftests: Allow for larger engine counts drm/i915/xehp: Extra media engines - Part 1 (engine definitions) drm/i915/xehp: Extra media engines - Part 2 (interrupts) drm/i915/xehp: Extra media engines - Part 3 (reset) José Roberto de Souza (1): drm/i915/dg2: Add DG2 to the PSR2 defeature list Lucas De Marchi (5): drm/i915: Add "release id" version drm/i915: Add XE_HP initial definitions drm/i915/xehpsdv: add initial XeHP SDV definitions drm/i915/xehpsdv: Define MOCS table for XeHP SDV drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper (29): drm/i915/xehp: Xe_HP forcewake support drm/i915/xehp: Define multicast register ranges drm/i915/xehp: Loop over all gslices for INSTDONE processing drm/i915/xehpsdv: Add maximum sseu limits drm/i915/xehpsdv: Define steering tables drm/i915/xehpsdv: Read correct RP_STATE_CAP register drm/i915/dg2: add DG2 platform info drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV drm/i915/dg2: Add forcewake table drm/i915/dg2: Update LNCF steering ranges drm/i915/dg2: Add SQIDI steering drm/i915/dg2: Maintain backward-compatible nested batch behavior drm/i915/dg2: Report INSTDONE_GEOM values in error state drm/i915/dg2: Define MOCS table for DG2 drm/i915/dg2: Add fake PCH drm/i915/dg2: Add cdclk table and reference clock drm/i915/dg2: Skip shared DPLL handling drm/i915/dg2: Don't wait for AUX power well enable ACKs drm/i915/dg2: Setup display outputs drm/i915/dg2: Add dbuf programming drm/i915/dg2: Don't program BW_BUDDY registers drm/i915/dg2: Don't read DRAM info drm/i915/dg2: DG2 has fixed memory bandwidth drm/i915/dg2: Add MPLLB programming for SNPS PHY drm/i915/dg2: Add MPLLB programming for HDMI drm/i915/dg2: Add vswing programming for SNPS phys drm/i915/dg2: Update modeset sequences drm/i915/dg2: Classify DG2 PHY types drm/i915/dg2: Wait for SNPS PHY calibration during display init Matthew Auld (1): drm/i915/xehp: Changes to ss/eu definitions Paulo Zanoni (1): drm/i915: Fork DG1 interrupt handler Prathap Kumar Valsan (1): drm/i915/xehp: New engine context offsets Stuart Summers (2): drm/i915/xehp: Handle new device context ID format drm/i915/xehpsdv: Add compute DSS type Tvrtko Ursulin (1): drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Venkata Sandeep Dhanalakota (1): drm/i915/gen12: Use fuse info to enable SFC drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 24 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +- drivers/gpu/drm/i915/display/intel_ddi.c | 165 +++- drivers/gpu/drm/i915/display/intel_display.c | 94 +- drivers/gpu/drm/i915/display/intel_display.h | 1 + .../drm/i915/display/intel_display_debugfs.c | 103 ++- .../drm/i915/display/intel_display_power.c | 25 + .../drm/i915/display/intel_display_power.h | 10 + .../drm/i915/display/intel_display_types.h | 18 +- drivers/gpu/drm/i915/display/intel_dp.c | 23 +- drivers/gpu/drm/i915/display/intel_dpll.c | 12 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 11 + drivers/gpu/drm/i915/display/intel_psr.c | 10 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 862 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_snps_phy.h | 35 + drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 144 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +- .../drm/i915/gt/intel_execlists_submission.c | 78 +- drivers/gpu/drm/i915/gt/intel_gt.c | 66 +- drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +++- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 + drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 6 + drivers/gpu/drm/i915/gt/intel_rps.c | 19 +- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 116 ++- drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 175 +++- drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 32 +- drivers/gpu/drm/i915/i915_debugfs.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 48 +- drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 36 +- drivers/gpu/drm/i915/i915_irq.c | 141 ++- drivers/gpu/drm/i915/i915_pci.c | 63 +- drivers/gpu/drm/i915/i915_perf.c | 29 +- drivers/gpu/drm/i915/i915_reg.h | 109 ++- drivers/gpu/drm/i915/intel_device_info.c | 4 + drivers/gpu/drm/i915/intel_device_info.h | 10 +- drivers/gpu/drm/i915/intel_dram.c | 6 +- drivers/gpu/drm/i915/intel_pch.c | 3 + drivers/gpu/drm/i915/intel_pch.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 120 ++- drivers/gpu/drm/i915/intel_step.c | 20 +- drivers/gpu/drm/i915/intel_step.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 367 ++++++-- drivers/gpu/drm/i915/intel_uncore.h | 14 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + include/uapi/drm/i915_drm.h | 3 - 59 files changed, 3085 insertions(+), 289 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h -- 2.25.4
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Lucas De Marchi <lucas.demarchi@intel.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Date: Thu, 1 Jul 2021 13:23:34 -0700 [thread overview] Message-ID: <20210701202427.1547543-1-matthew.d.roper@intel.com> (raw) This series provides some of the initial enablement patches for two upcoming discrete GPUs: * XeHP SDV: Xe_HP (version 12.50) graphics IP, no display IP * DG2: Xe_HPG (version 12.55) graphics IP, Xe_LPD (version 13) display IP Both platforms will need additional enablement patches beyond what's present in this series before they're truly usable, including various LMEM and GuC work that's already happening separately. The new features/functionality that these platforms bring (such as multi-tile support, dedicated compute engines, etc.) may be referenced in passing in some of these patches but will be fully enabled in future series. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Akeem G Abodunrin (1): drm/i915/dg2: Add new LRI reg offsets Animesh Manna (1): drm/i915/dg2: Update to bigjoiner path Ankit Nautiyal (1): drm/i915/dg2: Configure PCON in DP pre-enable path Anusha Srivatsa (2): drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable drm/i915/display/dsc: Set BPP in the kernel Daniele Ceraolo Spurio (1): drm/i915/xehp: handle new steering options Gwan-gyeong Mun (1): drm/i915/dg2: Update lane disable power state during PSR John Harrison (4): drm/i915/selftests: Allow for larger engine counts drm/i915/xehp: Extra media engines - Part 1 (engine definitions) drm/i915/xehp: Extra media engines - Part 2 (interrupts) drm/i915/xehp: Extra media engines - Part 3 (reset) José Roberto de Souza (1): drm/i915/dg2: Add DG2 to the PSR2 defeature list Lucas De Marchi (5): drm/i915: Add "release id" version drm/i915: Add XE_HP initial definitions drm/i915/xehpsdv: add initial XeHP SDV definitions drm/i915/xehpsdv: Define MOCS table for XeHP SDV drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper (29): drm/i915/xehp: Xe_HP forcewake support drm/i915/xehp: Define multicast register ranges drm/i915/xehp: Loop over all gslices for INSTDONE processing drm/i915/xehpsdv: Add maximum sseu limits drm/i915/xehpsdv: Define steering tables drm/i915/xehpsdv: Read correct RP_STATE_CAP register drm/i915/dg2: add DG2 platform info drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV drm/i915/dg2: Add forcewake table drm/i915/dg2: Update LNCF steering ranges drm/i915/dg2: Add SQIDI steering drm/i915/dg2: Maintain backward-compatible nested batch behavior drm/i915/dg2: Report INSTDONE_GEOM values in error state drm/i915/dg2: Define MOCS table for DG2 drm/i915/dg2: Add fake PCH drm/i915/dg2: Add cdclk table and reference clock drm/i915/dg2: Skip shared DPLL handling drm/i915/dg2: Don't wait for AUX power well enable ACKs drm/i915/dg2: Setup display outputs drm/i915/dg2: Add dbuf programming drm/i915/dg2: Don't program BW_BUDDY registers drm/i915/dg2: Don't read DRAM info drm/i915/dg2: DG2 has fixed memory bandwidth drm/i915/dg2: Add MPLLB programming for SNPS PHY drm/i915/dg2: Add MPLLB programming for HDMI drm/i915/dg2: Add vswing programming for SNPS phys drm/i915/dg2: Update modeset sequences drm/i915/dg2: Classify DG2 PHY types drm/i915/dg2: Wait for SNPS PHY calibration during display init Matthew Auld (1): drm/i915/xehp: Changes to ss/eu definitions Paulo Zanoni (1): drm/i915: Fork DG1 interrupt handler Prathap Kumar Valsan (1): drm/i915/xehp: New engine context offsets Stuart Summers (2): drm/i915/xehp: Handle new device context ID format drm/i915/xehpsdv: Add compute DSS type Tvrtko Ursulin (1): drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Venkata Sandeep Dhanalakota (1): drm/i915/gen12: Use fuse info to enable SFC drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_bw.c | 24 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 +- drivers/gpu/drm/i915/display/intel_ddi.c | 165 +++- drivers/gpu/drm/i915/display/intel_display.c | 94 +- drivers/gpu/drm/i915/display/intel_display.h | 1 + .../drm/i915/display/intel_display_debugfs.c | 103 ++- .../drm/i915/display/intel_display_power.c | 25 + .../drm/i915/display/intel_display_power.h | 10 + .../drm/i915/display/intel_display_types.h | 18 +- drivers/gpu/drm/i915/display/intel_dp.c | 23 +- drivers/gpu/drm/i915/display/intel_dpll.c | 12 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 11 + drivers/gpu/drm/i915/display/intel_psr.c | 10 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 862 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_snps_phy.h | 35 + drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 8 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 144 ++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +- .../drm/i915/gt/intel_execlists_submission.c | 78 +- drivers/gpu/drm/i915/gt/intel_gt.c | 66 +- drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 + drivers/gpu/drm/i915/gt/intel_lrc.c | 156 +++- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 2 + drivers/gpu/drm/i915/gt/intel_mocs.c | 66 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_reset.c | 6 + drivers/gpu/drm/i915/gt/intel_rps.c | 19 +- drivers/gpu/drm/i915/gt/intel_rps.h | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 116 ++- drivers/gpu/drm/i915/gt/intel_sseu.h | 20 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 175 +++- drivers/gpu/drm/i915/gt/selftest_execlists.c | 10 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 32 +- drivers/gpu/drm/i915/i915_debugfs.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 48 +- drivers/gpu/drm/i915/i915_getparam.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 36 +- drivers/gpu/drm/i915/i915_irq.c | 141 ++- drivers/gpu/drm/i915/i915_pci.c | 63 +- drivers/gpu/drm/i915/i915_perf.c | 29 +- drivers/gpu/drm/i915/i915_reg.h | 109 ++- drivers/gpu/drm/i915/intel_device_info.c | 4 + drivers/gpu/drm/i915/intel_device_info.h | 10 +- drivers/gpu/drm/i915/intel_dram.c | 6 +- drivers/gpu/drm/i915/intel_pch.c | 3 + drivers/gpu/drm/i915/intel_pch.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 120 ++- drivers/gpu/drm/i915/intel_step.c | 20 +- drivers/gpu/drm/i915/intel_step.h | 1 + drivers/gpu/drm/i915/intel_uncore.c | 367 ++++++-- drivers/gpu/drm/i915/intel_uncore.h | 14 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + include/uapi/drm/i915_drm.h | 3 - 59 files changed, 3085 insertions(+), 289 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.c create mode 100644 drivers/gpu/drm/i915/display/intel_snps_phy.h -- 2.25.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2021-07-01 20:25 UTC|newest] Thread overview: 173+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-01 20:23 Matt Roper [this message] 2021-07-01 20:23 ` [Intel-gfx] [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms Matt Roper 2021-07-01 20:23 ` [PATCH 01/53] drm/i915: Add "release id" version Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-02 12:33 ` Tvrtko Ursulin 2021-07-05 11:52 ` Jani Nikula 2021-07-05 11:52 ` Jani Nikula 2021-07-06 21:09 ` Lucas De Marchi 2021-07-06 21:09 ` Lucas De Marchi 2021-07-07 8:34 ` Jani Nikula 2021-07-07 8:34 ` Jani Nikula 2021-07-07 15:40 ` Lucas De Marchi 2021-07-07 15:40 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-06 20:57 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 02/53] drm/i915: Add XE_HP initial definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 03/53] drm/i915: Fork DG1 interrupt handler Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 9:21 ` Daniel Vetter 2021-07-02 9:21 ` [Intel-gfx] " Daniel Vetter 2021-07-06 22:48 ` Lucas De Marchi 2021-07-06 22:48 ` Lucas De Marchi 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 7:39 ` Daniel Vetter 2021-07-07 15:53 ` Lucas De Marchi 2021-07-07 15:53 ` Lucas De Marchi 2021-07-01 20:23 ` [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:06 ` Lucas De Marchi 2021-07-01 22:06 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:19 ` Lucas De Marchi 2021-07-01 22:19 ` Lucas De Marchi 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-02 12:08 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 22:33 ` Lucas De Marchi 2021-07-01 22:33 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:23 ` [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-02 12:22 ` Tvrtko Ursulin 2021-07-07 22:17 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-02 12:42 ` Tvrtko Ursulin 2021-07-06 21:15 ` Lucas De Marchi 2021-07-06 21:15 ` Lucas De Marchi 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-07 7:46 ` Tvrtko Ursulin 2021-07-01 20:23 ` [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset) Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 11/53] drm/i915/xehp: Define multicast register ranges Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 12/53] drm/i915/xehp: Handle new device context ID format Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 13/53] drm/i915/xehp: New engine context offsets Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 14/53] drm/i915/xehp: handle new steering options Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi 2021-07-02 7:57 ` Jani Nikula 2021-07-02 7:57 ` [Intel-gfx] " Jani Nikula 2021-07-07 22:20 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-01 20:23 ` [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 20/53] drm/i915/xehpsdv: Define steering tables Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 21:41 ` Rodrigo Vivi 2021-07-01 21:41 ` [Intel-gfx] " Rodrigo Vivi 2021-07-01 20:23 ` [PATCH 24/53] drm/i915/dg2: add DG2 platform info Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:23 ` [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV Matt Roper 2021-07-01 20:23 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 26/53] drm/i915/dg2: Add forcewake table Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 28/53] drm/i915/dg2: Add SQIDI steering Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:57 ` Lionel Landwerlin 2021-07-02 8:57 ` [Intel-gfx] " Lionel Landwerlin 2021-07-01 20:24 ` [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2 Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 33/53] drm/i915/dg2: Add fake PCH Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-06 21:47 ` Lucas De Marchi 2021-07-06 21:47 ` [Intel-gfx] " Lucas De Marchi 2021-07-01 20:24 ` [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 37/53] drm/i915/dg2: Setup display outputs Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 38/53] drm/i915/dg2: Add dbuf programming Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 40/53] drm/i915/dg2: Don't read DRAM info Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:14 ` Jani Nikula 2021-07-02 8:14 ` [Intel-gfx] " Jani Nikula 2021-07-01 20:24 ` [PATCH 45/53] drm/i915/dg2: Update modeset sequences Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:16 ` Jani Nikula 2021-07-02 8:16 ` Jani Nikula 2021-07-07 22:22 ` [Intel-gfx] [PATCH v2] " Matt Roper 2021-07-09 18:25 ` Lucas De Marchi 2021-07-01 20:24 ` [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 8:19 ` Jani Nikula 2021-07-02 8:19 ` [Intel-gfx] " Jani Nikula 2021-08-23 5:42 ` Kulkarni, Vandita 2021-08-23 5:42 ` [Intel-gfx] " Kulkarni, Vandita 2021-07-01 20:24 ` [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-01 20:24 ` [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-09 0:11 ` Navare, Manasi 2021-07-09 0:11 ` [Intel-gfx] " Navare, Manasi 2021-07-01 20:24 ` [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path Matt Roper 2021-07-01 20:24 ` [Intel-gfx] " Matt Roper 2021-07-02 1:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms Patchwork 2021-07-02 1:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-02 2:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-02 8:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-07 22:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev4) Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210701202427.1547543-1-matthew.d.roper@intel.com \ --to=matthew.d.roper@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=james.ausmus@intel.com \ --cc=lucas.demarchi@intel.com \ --cc=rodrigo.vivi@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.