From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>, Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> Subject: [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Date: Fri, 9 Jul 2021 18:20:14 -0700 [thread overview] Message-ID: <20210710012026.19705-5-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Declare header and source files for SLPC, along with init and enable/disable function templates. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 34 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 16 ++++++++++ 4 files changed, 53 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index ab7679957623..d8eac4468df9 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \ gt/uc/intel_guc_fw.o \ gt/uc/intel_guc_log.o \ gt/uc/intel_guc_log_debugfs.o \ + gt/uc/intel_guc_slpc.o \ gt/uc/intel_guc_submission.o \ gt/uc/intel_huc.o \ gt/uc/intel_huc_debugfs.o \ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index e5a456918b88..0dbbd9cf553f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -15,6 +15,7 @@ #include "intel_guc_ct.h" #include "intel_guc_log.h" #include "intel_guc_reg.h" +#include "intel_guc_slpc.h" #include "intel_uc_fw.h" #include "i915_utils.h" #include "i915_vma.h" @@ -30,6 +31,7 @@ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; + struct intel_guc_slpc slpc; /* Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c new file mode 100644 index 000000000000..c1f569d2300d --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2020 Intel Corporation + */ + +#include "intel_guc_slpc.h" + +int intel_guc_slpc_init(struct intel_guc_slpc *slpc) +{ + return 0; +} + +/* + * intel_guc_slpc_enable() - Start SLPC + * @slpc: pointer to intel_guc_slpc. + * + * SLPC is enabled by setting up the shared data structure and + * sending reset event to GuC SLPC. Initial data is setup in + * intel_guc_slpc_init. Here we send the reset event. We do + * not currently need a slpc_disable since this is taken care + * of automatically when a reset/suspend occurs and the guc + * channels are destroyed. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) +{ + return 0; +} + +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc) +{ +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h new file mode 100644 index 000000000000..74fd86769163 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2020 Intel Corporation + */ +#ifndef _INTEL_GUC_SLPC_H_ +#define _INTEL_GUC_SLPC_H_ + +struct intel_guc_slpc { +}; + +int intel_guc_slpc_init(struct intel_guc_slpc *slpc); +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); + +#endif -- 2.25.0
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From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Date: Fri, 9 Jul 2021 18:20:14 -0700 [thread overview] Message-ID: <20210710012026.19705-5-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210710012026.19705-1-vinay.belgaumkar@intel.com> Declare header and source files for SLPC, along with init and enable/disable function templates. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 34 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 16 ++++++++++ 4 files changed, 53 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index ab7679957623..d8eac4468df9 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \ gt/uc/intel_guc_fw.o \ gt/uc/intel_guc_log.o \ gt/uc/intel_guc_log_debugfs.o \ + gt/uc/intel_guc_slpc.o \ gt/uc/intel_guc_submission.o \ gt/uc/intel_huc.o \ gt/uc/intel_huc_debugfs.o \ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index e5a456918b88..0dbbd9cf553f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -15,6 +15,7 @@ #include "intel_guc_ct.h" #include "intel_guc_log.h" #include "intel_guc_reg.h" +#include "intel_guc_slpc.h" #include "intel_uc_fw.h" #include "i915_utils.h" #include "i915_vma.h" @@ -30,6 +31,7 @@ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; + struct intel_guc_slpc slpc; /* Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c new file mode 100644 index 000000000000..c1f569d2300d --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2020 Intel Corporation + */ + +#include "intel_guc_slpc.h" + +int intel_guc_slpc_init(struct intel_guc_slpc *slpc) +{ + return 0; +} + +/* + * intel_guc_slpc_enable() - Start SLPC + * @slpc: pointer to intel_guc_slpc. + * + * SLPC is enabled by setting up the shared data structure and + * sending reset event to GuC SLPC. Initial data is setup in + * intel_guc_slpc_init. Here we send the reset event. We do + * not currently need a slpc_disable since this is taken care + * of automatically when a reset/suspend occurs and the guc + * channels are destroyed. + * + * Return: 0 on success, non-zero error code on failure. + */ +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) +{ + return 0; +} + +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc) +{ +} diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h new file mode 100644 index 000000000000..74fd86769163 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2020 Intel Corporation + */ +#ifndef _INTEL_GUC_SLPC_H_ +#define _INTEL_GUC_SLPC_H_ + +struct intel_guc_slpc { +}; + +int intel_guc_slpc_init(struct intel_guc_slpc *slpc); +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); + +#endif -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-10 1:23 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-10 1:20 [PATCH 00/16] Enable GuC based power management features Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] [PATCH 01/16] drm/i915/guc: Squashed patch - DO NOT REVIEW Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 02/16] drm/i915/guc/slpc: Initial definitions for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 14:27 ` Michal Wajdeczko 2021-07-10 14:27 ` [Intel-gfx] " Michal Wajdeczko 2021-07-12 18:40 ` Belgaumkar, Vinay 2021-07-12 18:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-12 23:43 ` Belgaumkar, Vinay 2021-07-12 23:43 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 03/16] drm/i915/guc/slpc: Gate Host RPS when slpc is enabled Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` Vinay Belgaumkar [this message] 2021-07-10 1:20 ` [Intel-gfx] [PATCH 04/16] drm/i915/guc/slpc: Lay out slpc init/enable/disable/fini Vinay Belgaumkar 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-10 14:35 ` Michal Wajdeczko 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-13 0:37 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 05/16] drm/i915/guc/slpc: Adding slpc communication interfaces Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 15:52 ` Michal Wajdeczko 2021-07-10 15:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-13 23:22 ` Belgaumkar, Vinay 2021-07-13 23:22 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 06/16] drm/i915/guc/slpc: Allocate, initialize and release slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 16:05 ` Michal Wajdeczko 2021-07-10 16:05 ` [Intel-gfx] " Michal Wajdeczko 2021-07-14 1:40 ` Belgaumkar, Vinay 2021-07-14 1:40 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 07/16] drm/i915/guc/slpc: Enable slpc and add related H2G events Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-10 17:37 ` Michal Wajdeczko 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-15 1:58 ` Belgaumkar, Vinay 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-21 17:36 ` Michal Wajdeczko 2021-07-10 1:20 ` [PATCH 08/16] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` kernel test robot 2021-07-10 3:07 ` [Intel-gfx] " kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` kernel test robot 2021-07-10 5:17 ` [Intel-gfx] " kernel test robot 2021-07-10 17:47 ` Michal Wajdeczko 2021-07-10 17:47 ` [Intel-gfx] " Michal Wajdeczko 2021-07-16 18:00 ` Belgaumkar, Vinay 2021-07-16 18:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 09/16] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 17:52 ` Michal Wajdeczko 2021-07-10 17:52 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 22:08 ` Belgaumkar, Vinay 2021-07-20 22:08 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 10/16] drm/i915/guc/slpc: Add debugfs for slpc info Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:08 ` Michal Wajdeczko 2021-07-10 18:08 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:00 ` Belgaumkar, Vinay 2021-07-20 23:00 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 11/16] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 12/16] drm/i915/guc/slpc: Cache platform frequency limits for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-10 18:15 ` Michal Wajdeczko 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-17 19:30 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-20 23:05 ` Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 13/16] drm/i915/guc/slpc: Update slpc to use platform min/max Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 1:20 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` kernel test robot 2021-07-10 6:18 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 7:30 ` [RFC PATCH] drm/i915/guc/slpc: intel_rps_read_punit_req() can be static kernel test robot 2021-07-10 7:30 ` kernel test robot 2021-07-10 7:30 ` [Intel-gfx] " kernel test robot 2021-07-10 13:54 ` [PATCH 14/16] drm/i915/guc/slpc: Sysfs hooks for slpc kernel test robot 2021-07-10 13:54 ` kernel test robot 2021-07-10 13:54 ` [Intel-gfx] " kernel test robot 2021-07-10 18:20 ` Michal Wajdeczko 2021-07-10 18:20 ` [Intel-gfx] " Michal Wajdeczko 2021-07-20 23:38 ` Belgaumkar, Vinay 2021-07-20 23:38 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 15/16] drm/i915/guc/slpc: slpc selftest Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:29 ` Michal Wajdeczko 2021-07-10 18:29 ` [Intel-gfx] " Michal Wajdeczko 2021-07-21 1:06 ` Belgaumkar, Vinay 2021-07-21 1:06 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-10 1:20 ` [PATCH 16/16] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar 2021-07-10 1:20 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-10 18:41 ` Michal Wajdeczko 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-21 1:11 ` Belgaumkar, Vinay 2021-07-10 1:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable GuC based power management features Patchwork 2021-07-10 1:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-10 2:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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