From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org
Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org,
perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com,
bgoswami@codeaurora.org,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Subject: [PATCH v3 20/20] ASoC: qdsp6: audioreach: add support for q6prm-clocks
Date: Tue, 3 Aug 2021 13:54:11 +0100 [thread overview]
Message-ID: <20210803125411.28066-21-srinivas.kandagatla@linaro.org> (raw)
In-Reply-To: <20210803125411.28066-1-srinivas.kandagatla@linaro.org>
Add q6prm clocks using existing qdsp6-audio-clock driver
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
sound/soc/qcom/Kconfig | 4 ++
sound/soc/qcom/qdsp6/Makefile | 2 +
sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 +++++++++++++++++++++++++++++
sound/soc/qcom/qdsp6/q6prm.h | 78 ++++++++++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c
create mode 100644 sound/soc/qcom/qdsp6/q6prm.h
diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
index e9155c4022b4..817da5628fc0 100644
--- a/sound/soc/qcom/Kconfig
+++ b/sound/soc/qcom/Kconfig
@@ -112,6 +112,9 @@ config SND_SOC_QDSP6_APM_BEDAI
config SND_SOC_QDSP6_PRM
tristate
+config SND_SOC_QDSP6_PRM_CLOCKS
+ tristate
+
config SND_SOC_QDSP6_AUDIOREACH
tristate "SoC ALSA audio drives for Qualcomm QDSP AUDIOREACH Framework"
depends on QCOM_GPR
@@ -119,6 +122,7 @@ config SND_SOC_QDSP6_AUDIOREACH
select SND_SOC_QDSP6_APM_DAI
select SND_SOC_QDSP6_APM_BEDAI
select SND_SOC_QDSP6_PRM
+ select SND_SOC_QDSP6_PRM_CLOCKS
help
To add support for Qualcomm QDSP6 AudioReach Audio Framework.
This will enable sound soc platform specific audio drivers.
diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile
index 0388b1c10eb1..65ac31770051 100644
--- a/sound/soc/qcom/qdsp6/Makefile
+++ b/sound/soc/qcom/qdsp6/Makefile
@@ -3,6 +3,7 @@ snd-ar-objs := audioreach.o q6apm.o topology.o
snd-apm-dai-objs := q6apm-dai.o
snd-apm-bedai-objs := q6dsp-audio-ports.o q6apm-bedai.o
snd-prm-objs := q6prm.o
+snd-prm-clks-objs := q6dsp-audio-clocks.o q6prm-clocks.o
snd-afe-dai-objs += q6dsp-audio-ports.o q6afe-dai.o
snd-afe-clks-objs := q6dsp-audio-clocks.o q6afe-clocks.o
@@ -21,3 +22,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_AUDIOREACH) += snd-ar.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += snd-apm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_BEDAI) += snd-apm-bedai.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM) += snd-prm.o
+obj-$(CONFIG_SND_SOC_QDSP6_PRM_CLOCKS) += snd-prm-clks.o
diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
new file mode 100644
index 000000000000..1735d5c0c0af
--- /dev/null
+++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021, Linaro Limited
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/sound/qcom,q6dsp-audio-ports.h>
+#include "q6dsp-audio-clocks.h"
+#include "q6prm.h"
+
+#define Q6PRM_CLK(id) { \
+ .clk_id = id, \
+ .q6dsp_clk_id = Q6PRM_##id, \
+ .name = #id, \
+ .rate = 19200000, \
+ }
+
+static const struct q6dsp_clk_init q6prm_clks[] = {
+ Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
+ Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
+ Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
+ "LPASS_HW_MACRO"),
+ Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
+ "LPASS_HW_DCODEC"),
+};
+
+static const struct q6dsp_clk_desc q6dsp_clk_q6prm = {
+ .clks = q6prm_clks,
+ .num_clks = ARRAY_SIZE(q6prm_clks),
+ .lpass_set_clk = q6prm_set_lpass_clock,
+ .lpass_vote_clk = q6prm_vote_lpass_core_hw,
+ .lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id q6prm_clock_device_id[] = {
+ { .compatible = "qcom,q6prm-clocks", .data = &q6dsp_clk_q6prm },
+ {},
+};
+MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
+#endif
+
+static struct platform_driver q6prm_clock_platform_driver = {
+ .driver = {
+ .name = "q6prm-clock",
+ .of_match_table = of_match_ptr(q6prm_clock_device_id),
+ },
+ .probe = q6dsp_clock_dev_probe,
+};
+module_platform_driver(q6prm_clock_platform_driver);
+
+MODULE_DESCRIPTION("Q6 Proxy Resource Manager clock driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
new file mode 100644
index 000000000000..91ec535e8564
--- /dev/null
+++ b/sound/soc/qcom/qdsp6/q6prm.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __Q6PRM_H__
+#define __Q6PRM_H__
+
+/* Clock ID for Primary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
+/* Clock ID for Primary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
+/* Clock ID for Secondary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
+/* Clock ID for Secondary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
+/* Clock ID for Tertiary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
+/* Clock ID for Tertiary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
+/* Clock ID for Quartnery I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
+/* Clock ID for Quartnery I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
+/* Clock ID for Speaker I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
+/* Clock ID for Speaker I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
+/* Clock ID for Speaker I2S OSR */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
+
+/* Clock ID for QUINARY I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
+/* Clock ID for QUINARY I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
+/* Clock ID for SENARY I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
+/* Clock ID for SENARY I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
+/* Clock ID for INT0 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
+/* Clock ID for INT1 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
+/* Clock ID for INT2 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
+/* Clock ID for INT3 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
+/* Clock ID for INT4 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
+/* Clock ID for INT5 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
+/* Clock ID for INT6 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
+
+/* Clock ID for QUINARY MI2S OSR CLK */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
+
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
+
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
+
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
+
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
+
+#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
+#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
+#define Q6PRM_HW_CORE_ID_LPASS 1
+#define Q6PRM_HW_CORE_ID_DCODEC 2
+
+int q6prm_set_lpass_clock(struct device *dev, int clk_id, int attri,
+ int clk_root, unsigned int freq);
+int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+ const char *client_name, uint32_t *client_handle);
+int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+ uint32_t client_handle);
+#endif /* __Q6PRM_H__ */
--
2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org
Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org,
bgoswami@codeaurora.org, tiwai@suse.de, plai@codeaurora.org,
lgirdwood@gmail.com
Subject: [PATCH v3 20/20] ASoC: qdsp6: audioreach: add support for q6prm-clocks
Date: Tue, 3 Aug 2021 13:54:11 +0100 [thread overview]
Message-ID: <20210803125411.28066-21-srinivas.kandagatla@linaro.org> (raw)
In-Reply-To: <20210803125411.28066-1-srinivas.kandagatla@linaro.org>
Add q6prm clocks using existing qdsp6-audio-clock driver
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
sound/soc/qcom/Kconfig | 4 ++
sound/soc/qcom/qdsp6/Makefile | 2 +
sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 +++++++++++++++++++++++++++++
sound/soc/qcom/qdsp6/q6prm.h | 78 ++++++++++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c
create mode 100644 sound/soc/qcom/qdsp6/q6prm.h
diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig
index e9155c4022b4..817da5628fc0 100644
--- a/sound/soc/qcom/Kconfig
+++ b/sound/soc/qcom/Kconfig
@@ -112,6 +112,9 @@ config SND_SOC_QDSP6_APM_BEDAI
config SND_SOC_QDSP6_PRM
tristate
+config SND_SOC_QDSP6_PRM_CLOCKS
+ tristate
+
config SND_SOC_QDSP6_AUDIOREACH
tristate "SoC ALSA audio drives for Qualcomm QDSP AUDIOREACH Framework"
depends on QCOM_GPR
@@ -119,6 +122,7 @@ config SND_SOC_QDSP6_AUDIOREACH
select SND_SOC_QDSP6_APM_DAI
select SND_SOC_QDSP6_APM_BEDAI
select SND_SOC_QDSP6_PRM
+ select SND_SOC_QDSP6_PRM_CLOCKS
help
To add support for Qualcomm QDSP6 AudioReach Audio Framework.
This will enable sound soc platform specific audio drivers.
diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile
index 0388b1c10eb1..65ac31770051 100644
--- a/sound/soc/qcom/qdsp6/Makefile
+++ b/sound/soc/qcom/qdsp6/Makefile
@@ -3,6 +3,7 @@ snd-ar-objs := audioreach.o q6apm.o topology.o
snd-apm-dai-objs := q6apm-dai.o
snd-apm-bedai-objs := q6dsp-audio-ports.o q6apm-bedai.o
snd-prm-objs := q6prm.o
+snd-prm-clks-objs := q6dsp-audio-clocks.o q6prm-clocks.o
snd-afe-dai-objs += q6dsp-audio-ports.o q6afe-dai.o
snd-afe-clks-objs := q6dsp-audio-clocks.o q6afe-clocks.o
@@ -21,3 +22,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_AUDIOREACH) += snd-ar.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += snd-apm-dai.o
obj-$(CONFIG_SND_SOC_QDSP6_APM_BEDAI) += snd-apm-bedai.o
obj-$(CONFIG_SND_SOC_QDSP6_PRM) += snd-prm.o
+obj-$(CONFIG_SND_SOC_QDSP6_PRM_CLOCKS) += snd-prm-clks.o
diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
new file mode 100644
index 000000000000..1735d5c0c0af
--- /dev/null
+++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021, Linaro Limited
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/sound/qcom,q6dsp-audio-ports.h>
+#include "q6dsp-audio-clocks.h"
+#include "q6prm.h"
+
+#define Q6PRM_CLK(id) { \
+ .clk_id = id, \
+ .q6dsp_clk_id = Q6PRM_##id, \
+ .name = #id, \
+ .rate = 19200000, \
+ }
+
+static const struct q6dsp_clk_init q6prm_clks[] = {
+ Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
+ Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
+ Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
+ "LPASS_HW_MACRO"),
+ Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
+ "LPASS_HW_DCODEC"),
+};
+
+static const struct q6dsp_clk_desc q6dsp_clk_q6prm = {
+ .clks = q6prm_clks,
+ .num_clks = ARRAY_SIZE(q6prm_clks),
+ .lpass_set_clk = q6prm_set_lpass_clock,
+ .lpass_vote_clk = q6prm_vote_lpass_core_hw,
+ .lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id q6prm_clock_device_id[] = {
+ { .compatible = "qcom,q6prm-clocks", .data = &q6dsp_clk_q6prm },
+ {},
+};
+MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
+#endif
+
+static struct platform_driver q6prm_clock_platform_driver = {
+ .driver = {
+ .name = "q6prm-clock",
+ .of_match_table = of_match_ptr(q6prm_clock_device_id),
+ },
+ .probe = q6dsp_clock_dev_probe,
+};
+module_platform_driver(q6prm_clock_platform_driver);
+
+MODULE_DESCRIPTION("Q6 Proxy Resource Manager clock driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
new file mode 100644
index 000000000000..91ec535e8564
--- /dev/null
+++ b/sound/soc/qcom/qdsp6/q6prm.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __Q6PRM_H__
+#define __Q6PRM_H__
+
+/* Clock ID for Primary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
+/* Clock ID for Primary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
+/* Clock ID for Secondary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
+/* Clock ID for Secondary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
+/* Clock ID for Tertiary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
+/* Clock ID for Tertiary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
+/* Clock ID for Quartnery I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
+/* Clock ID for Quartnery I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
+/* Clock ID for Speaker I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
+/* Clock ID for Speaker I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
+/* Clock ID for Speaker I2S OSR */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A
+
+/* Clock ID for QUINARY I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B
+/* Clock ID for QUINARY I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C
+/* Clock ID for SENARY I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D
+/* Clock ID for SENARY I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E
+/* Clock ID for INT0 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F
+/* Clock ID for INT1 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110
+/* Clock ID for INT2 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111
+/* Clock ID for INT3 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112
+/* Clock ID for INT4 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113
+/* Clock ID for INT5 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114
+/* Clock ID for INT6 I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115
+
+/* Clock ID for QUINARY MI2S OSR CLK */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
+
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
+
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
+
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
+
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
+
+#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
+#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
+#define Q6PRM_HW_CORE_ID_LPASS 1
+#define Q6PRM_HW_CORE_ID_DCODEC 2
+
+int q6prm_set_lpass_clock(struct device *dev, int clk_id, int attri,
+ int clk_root, unsigned int freq);
+int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+ const char *client_name, uint32_t *client_handle);
+int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+ uint32_t client_handle);
+#endif /* __Q6PRM_H__ */
--
2.21.0
next prev parent reply other threads:[~2021-08-03 12:54 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-03 12:53 [PATCH v3 00/20] ASoC: qcom: Add AudioReach support Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 01/20] soc: dt-bindings: qcom: apr: convert to yaml Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 02/20] soc: qcom: apr: make code more reuseable Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 03/20] soc: dt-bindings: qcom: add gpr bindings Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 04/20] soc: qcom: apr: Add GPR support Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 05/20] ASoC: dt-bindings: replace q6afe bindings with q6dsp-audio-ports Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-04 17:53 ` Mark Brown
2021-08-04 17:53 ` Mark Brown
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-11 18:19 ` Rob Herring
2021-08-11 18:19 ` Rob Herring
2021-08-03 12:53 ` [PATCH v3 06/20] ASoC: dt-bindings: replace q6afe-clk with q6dsp audio clk bindings Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-11 18:24 ` Rob Herring
2021-08-11 18:24 ` Rob Herring
2021-08-03 12:53 ` [PATCH v3 07/20] ASoC: dt-bindings: replace q6asm with q6dsp audio stream bindings Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:53 ` [PATCH v3 08/20] ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file Srinivas Kandagatla
2021-08-03 12:53 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 09/20] ASoC: qdsp6: q6afe-clocks: move audio-clocks " Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 10/20] ASoC: dt-bindings: q6dsp: add q6apm-dai compatible Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-04 18:01 ` Mark Brown
2021-08-04 18:01 ` Mark Brown
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 11/20] ASoC: dt-bindings: q6dsp: add q6apm-bedai compatible Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-04 18:01 ` Mark Brown
2021-08-04 18:01 ` Mark Brown
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-05 9:16 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 12/20] ASoC: dt-bindings: q6dsp-clocks: add q6prm clocks compatible Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-04 18:02 ` Mark Brown
2021-08-04 18:02 ` Mark Brown
2021-08-05 9:17 ` Srinivas Kandagatla
2021-08-05 9:17 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 13/20] ASoC: qdsp6: audioreach: add basic pkt alloc support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 14:19 ` Amadeusz Sławiński
2021-08-03 14:39 ` Srinivas Kandagatla
2021-08-04 18:09 ` Mark Brown
2021-08-04 18:09 ` Mark Brown
2021-08-05 9:17 ` Srinivas Kandagatla
2021-08-05 9:17 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 14/20] ASoC: qdsp6: audioreach: add q6apm support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 14:20 ` Amadeusz Sławiński
2021-08-03 14:48 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 15/20] ASoC: qdsp6: audioreach: add module configuration command helpers Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 16/20] ASoC: qdsp6: audioreach: add topology support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 14:21 ` Amadeusz Sławiński
2021-08-03 14:47 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 17/20] ASoC: qdsp6: audioreach: add q6apm-dai support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 18/20] ASoC: qdsp6: audioreach: add bedai support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 12:54 ` [PATCH v3 19/20] ASoC: qdsp6: audioreach: add q6prm support Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla
2021-08-03 12:54 ` Srinivas Kandagatla [this message]
2021-08-03 12:54 ` [PATCH v3 20/20] ASoC: qdsp6: audioreach: add support for q6prm-clocks Srinivas Kandagatla
2021-08-03 15:00 ` [PATCH v3 00/20] ASoC: qcom: Add AudioReach support Pierre-Louis Bossart
2021-08-03 15:03 ` Srinivas Kandagatla
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