From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB Date: Thu, 5 Aug 2021 10:53:11 +0800 [thread overview] Message-ID: <20210805025312.15720-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++------ target/riscv/translate.c | 8 +++++ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0bae0a2bbf..5de24c3a24 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -20,19 +20,19 @@ static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_clz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_clzw : gen_clz); } static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_ctz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_ctzw : gen_ctz); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ctpop_tl); + return gen_unary(ctx, a, ctx->uxl32 ? gen_cpopw : tcg_gen_ctpop_tl); } static bool trans_andn(DisasContext *ctx, arg_andn *a) @@ -56,43 +56,43 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) static bool trans_pack(DisasContext *ctx, arg_pack *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packw : gen_pack); } static bool trans_packu(DisasContext *ctx, arg_packu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packuw : gen_packu); } static bool trans_packh(DisasContext *ctx, arg_packh *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packhw : gen_packh); } static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smin_tl); + return gen_arith_s(ctx, a, tcg_gen_smin_tl); } static bool trans_max(DisasContext *ctx, arg_max *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smax_tl); + return gen_arith_s(ctx, a, tcg_gen_smax_tl); } static bool trans_minu(DisasContext *ctx, arg_minu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umin_tl); + return gen_arith_u(ctx, a, tcg_gen_umin_tl); } static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umax_tl); + return gen_arith_u(ctx, a, tcg_gen_umax_tl); } static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) @@ -170,36 +170,54 @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a) static bool trans_sro(DisasContext *ctx, arg_sro *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_srow(ctx, a); + } return gen_shift(ctx, a, gen_sro); } static bool trans_sroi(DisasContext *ctx, arg_sroi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_sroiw(ctx, a); + } return gen_shifti(ctx, a, gen_sro); } static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rorw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotr_tl); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_roriw(ctx, a); + } return gen_shifti(ctx, a, tcg_gen_rotr_tl); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rolw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotl_tl); } static bool trans_grev(DisasContext *ctx, arg_grev *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevw(ctx, a); + } return gen_shift(ctx, a, gen_helper_grev); } @@ -207,6 +225,9 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevi(ctx, a); + } if (a->shamt >= TARGET_LONG_BITS) { return false; } @@ -217,12 +238,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) static bool trans_gorc(DisasContext *ctx, arg_gorc *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorcw(ctx, a); + } return gen_shift(ctx, a, gen_helper_gorc); } static bool trans_gorci(DisasContext *ctx, arg_gorci *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorciw(ctx, a); + } return gen_shifti(ctx, a, gen_helper_gorc); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5ee0feac4b..f4b2f75812 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -742,6 +742,14 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } +static void gen_packhw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t = tcg_temp_new(); + tcg_gen_ext8u_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 8, 24); + tcg_temp_free(t); +} + static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32(); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB Date: Thu, 5 Aug 2021 10:53:11 +0800 [thread overview] Message-ID: <20210805025312.15720-13-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++------ target/riscv/translate.c | 8 +++++ 2 files changed, 45 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0bae0a2bbf..5de24c3a24 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -20,19 +20,19 @@ static bool trans_clz(DisasContext *ctx, arg_clz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_clz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_clzw : gen_clz); } static bool trans_ctz(DisasContext *ctx, arg_ctz *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, gen_ctz); + return gen_unary(ctx, a, ctx->uxl32 ? gen_ctzw : gen_ctz); } static bool trans_cpop(DisasContext *ctx, arg_cpop *a) { REQUIRE_EXT(ctx, RVB); - return gen_unary(ctx, a, tcg_gen_ctpop_tl); + return gen_unary(ctx, a, ctx->uxl32 ? gen_cpopw : tcg_gen_ctpop_tl); } static bool trans_andn(DisasContext *ctx, arg_andn *a) @@ -56,43 +56,43 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) static bool trans_pack(DisasContext *ctx, arg_pack *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packw : gen_pack); } static bool trans_packu(DisasContext *ctx, arg_packu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packuw : gen_packu); } static bool trans_packh(DisasContext *ctx, arg_packh *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); + return gen_arith(ctx, a, ctx->uxl32 ? gen_packhw : gen_packh); } static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smin_tl); + return gen_arith_s(ctx, a, tcg_gen_smin_tl); } static bool trans_max(DisasContext *ctx, arg_max *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_smax_tl); + return gen_arith_s(ctx, a, tcg_gen_smax_tl); } static bool trans_minu(DisasContext *ctx, arg_minu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umin_tl); + return gen_arith_u(ctx, a, tcg_gen_umin_tl); } static bool trans_maxu(DisasContext *ctx, arg_maxu *a) { REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, tcg_gen_umax_tl); + return gen_arith_u(ctx, a, tcg_gen_umax_tl); } static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a) @@ -170,36 +170,54 @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a) static bool trans_sro(DisasContext *ctx, arg_sro *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_srow(ctx, a); + } return gen_shift(ctx, a, gen_sro); } static bool trans_sroi(DisasContext *ctx, arg_sroi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_sroiw(ctx, a); + } return gen_shifti(ctx, a, gen_sro); } static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rorw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotr_tl); } static bool trans_rori(DisasContext *ctx, arg_rori *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_roriw(ctx, a); + } return gen_shifti(ctx, a, tcg_gen_rotr_tl); } static bool trans_rol(DisasContext *ctx, arg_rol *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_rolw(ctx, a); + } return gen_shift(ctx, a, tcg_gen_rotl_tl); } static bool trans_grev(DisasContext *ctx, arg_grev *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevw(ctx, a); + } return gen_shift(ctx, a, gen_helper_grev); } @@ -207,6 +225,9 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_grevi(ctx, a); + } if (a->shamt >= TARGET_LONG_BITS) { return false; } @@ -217,12 +238,18 @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a) static bool trans_gorc(DisasContext *ctx, arg_gorc *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorcw(ctx, a); + } return gen_shift(ctx, a, gen_helper_gorc); } static bool trans_gorci(DisasContext *ctx, arg_gorci *a) { REQUIRE_EXT(ctx, RVB); + if (ctx->uxl32) { + return trans_gorciw(ctx, a); + } return gen_shifti(ctx, a, gen_helper_gorc); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5ee0feac4b..f4b2f75812 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -742,6 +742,14 @@ static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } +static void gen_packhw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv t = tcg_temp_new(); + tcg_gen_ext8u_tl(t, arg2); + tcg_gen_deposit_tl(ret, arg1, t, 8, 24); + tcg_temp_free(t); +} + static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32(); -- 2.17.1
next prev parent reply other threads:[~2021-08-05 3:04 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei 2021-08-05 2:52 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 6:00 ` Alistair Francis 2021-08-05 6:00 ` Alistair Francis 2021-08-05 19:01 ` Richard Henderson 2021-08-05 19:01 ` Richard Henderson 2021-08-06 2:49 ` LIU Zhiwei 2021-08-06 2:49 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:06 ` Richard Henderson 2021-08-05 19:06 ` Richard Henderson 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 19:34 ` Richard Henderson 2021-08-09 19:34 ` Richard Henderson 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 17:56 ` Richard Henderson 2021-08-11 17:56 ` Richard Henderson 2021-08-11 22:40 ` LIU Zhiwei 2021-08-11 22:40 ` LIU Zhiwei 2021-08-12 4:42 ` Richard Henderson 2021-08-12 4:42 ` Richard Henderson 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 6:12 ` Richard Henderson 2021-08-12 6:12 ` Richard Henderson 2021-08-12 7:20 ` LIU Zhiwei 2021-08-12 7:20 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:08 ` Richard Henderson 2021-08-05 19:08 ` Richard Henderson 2021-08-09 1:50 ` LIU Zhiwei 2021-08-09 1:50 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:09 ` Richard Henderson 2021-08-05 19:09 ` Richard Henderson 2021-08-09 7:28 ` LIU Zhiwei 2021-08-09 7:28 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 22:17 ` Richard Henderson 2021-08-05 22:17 ` Richard Henderson 2021-08-09 7:51 ` LIU Zhiwei 2021-08-09 7:51 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 22:18 ` Richard Henderson 2021-08-05 22:18 ` Richard Henderson 2021-08-09 7:53 ` LIU Zhiwei 2021-08-09 7:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei [this message] 2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis 2021-08-05 6:01 ` Alistair Francis 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:20 ` Bin Meng 2021-08-05 7:20 ` Bin Meng 2021-08-05 8:10 ` LIU Zhiwei 2021-08-05 8:10 ` LIU Zhiwei 2021-08-06 10:05 ` Alistair Francis 2021-08-06 10:05 ` Alistair Francis 2021-08-09 1:25 ` LIU Zhiwei 2021-08-09 1:25 ` LIU Zhiwei
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