From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 01/13] target/riscv: Add UXL to tb flags Date: Thu, 5 Aug 2021 10:53:00 +0800 [thread overview] Message-ID: <20210805025312.15720-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> For 32-bit applications run on 64-bit cpu, it may share some code with other 64-bit applictions. Thus we should distinguish the translated cache of the share code with a tb flag. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/translate.c | 3 +++ 2 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..2b3ba21a78 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -394,9 +394,20 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, UXL, 10, 2) bool riscv_cpu_is_32bit(CPURISCVState *env); +static inline bool riscv_cpu_is_uxl32(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + return (get_field(env->mstatus, MSTATUS64_UXL) == 1) && + !riscv_cpu_is_32bit(env) && + (env->priv == PRV_U); +#endif + return false; +} + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) @@ -451,6 +462,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_cpu_is_uxl32(env)) { + flags = FIELD_DP32(flags, TB_FLAGS, UXL, + get_field(env->mstatus, MSTATUS64_UXL)); + } #endif *pflags = flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 076f28b9c1..ac4a545da8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,6 +67,8 @@ typedef struct DisasContext { CPUState *cs; TCGv zero; TCGv sink; + /* UXLEN is 32 bit for 64-bit CPU */ + bool uxl32; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -912,6 +914,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs = cs; + ctx->uxl32 = FIELD_EX32(tb_flags, TB_FLAGS, UXL) == 1; } static void riscv_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [RFC PATCH 01/13] target/riscv: Add UXL to tb flags Date: Thu, 5 Aug 2021 10:53:00 +0800 [thread overview] Message-ID: <20210805025312.15720-2-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210805025312.15720-1-zhiwei_liu@c-sky.com> For 32-bit applications run on 64-bit cpu, it may share some code with other 64-bit applictions. Thus we should distinguish the translated cache of the share code with a tb flag. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/cpu.h | 15 +++++++++++++++ target/riscv/translate.c | 3 +++ 2 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..2b3ba21a78 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -394,9 +394,20 @@ FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, UXL, 10, 2) bool riscv_cpu_is_32bit(CPURISCVState *env); +static inline bool riscv_cpu_is_uxl32(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + return (get_field(env->mstatus, MSTATUS64_UXL) == 1) && + !riscv_cpu_is_32bit(env) && + (env->priv == PRV_U); +#endif + return false; +} + /* * A simplification for VLMAX * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) @@ -451,6 +462,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + if (riscv_cpu_is_uxl32(env)) { + flags = FIELD_DP32(flags, TB_FLAGS, UXL, + get_field(env->mstatus, MSTATUS64_UXL)); + } #endif *pflags = flags; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 076f28b9c1..ac4a545da8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,6 +67,8 @@ typedef struct DisasContext { CPUState *cs; TCGv zero; TCGv sink; + /* UXLEN is 32 bit for 64-bit CPU */ + bool uxl32; } DisasContext; static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -912,6 +914,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs = cs; + ctx->uxl32 = FIELD_EX32(tb_flags, TB_FLAGS, UXL) == 1; } static void riscv_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) -- 2.17.1
next prev parent reply other threads:[~2021-08-05 2:56 UTC|newest] Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei 2021-08-05 2:52 ` LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei [this message] 2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei 2021-08-05 6:00 ` Alistair Francis 2021-08-05 6:00 ` Alistair Francis 2021-08-05 19:01 ` Richard Henderson 2021-08-05 19:01 ` Richard Henderson 2021-08-06 2:49 ` LIU Zhiwei 2021-08-06 2:49 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:06 ` Richard Henderson 2021-08-05 19:06 ` Richard Henderson 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 1:45 ` LIU Zhiwei 2021-08-09 19:34 ` Richard Henderson 2021-08-09 19:34 ` Richard Henderson 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 14:57 ` LIU Zhiwei 2021-08-11 17:56 ` Richard Henderson 2021-08-11 17:56 ` Richard Henderson 2021-08-11 22:40 ` LIU Zhiwei 2021-08-11 22:40 ` LIU Zhiwei 2021-08-12 4:42 ` Richard Henderson 2021-08-12 4:42 ` Richard Henderson 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 5:03 ` LIU Zhiwei 2021-08-12 6:12 ` Richard Henderson 2021-08-12 6:12 ` Richard Henderson 2021-08-12 7:20 ` LIU Zhiwei 2021-08-12 7:20 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:08 ` Richard Henderson 2021-08-05 19:08 ` Richard Henderson 2021-08-09 1:50 ` LIU Zhiwei 2021-08-09 1:50 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 19:09 ` Richard Henderson 2021-08-05 19:09 ` Richard Henderson 2021-08-09 7:28 ` LIU Zhiwei 2021-08-09 7:28 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 22:17 ` Richard Henderson 2021-08-05 22:17 ` Richard Henderson 2021-08-09 7:51 ` LIU Zhiwei 2021-08-09 7:51 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 22:18 ` Richard Henderson 2021-08-05 22:18 ` Richard Henderson 2021-08-09 7:53 ` LIU Zhiwei 2021-08-09 7:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei 2021-08-05 2:53 ` LIU Zhiwei 2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis 2021-08-05 6:01 ` Alistair Francis 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:14 ` LIU Zhiwei 2021-08-05 7:20 ` Bin Meng 2021-08-05 7:20 ` Bin Meng 2021-08-05 8:10 ` LIU Zhiwei 2021-08-05 8:10 ` LIU Zhiwei 2021-08-06 10:05 ` Alistair Francis 2021-08-06 10:05 ` Alistair Francis 2021-08-09 1:25 ` LIU Zhiwei 2021-08-09 1:25 ` LIU Zhiwei
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