From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Nanley G Chery <nanley.g.chery@intel.com>, Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>, dri-devel@lists.freedesktop.org Subject: [PATCH v2 6/6] drm/fourcc: Add the ADL-P specific pitch requirements of CCS modifiers Date: Mon, 6 Sep 2021 21:27:15 +0300 [thread overview] Message-ID: <20210906182715.3915100-7-imre.deak@intel.com> (raw) In-Reply-To: <20210906182715.3915100-1-imre.deak@intel.com> On Alderlake-P for all CCS modifiers the main surface pitch must be either 8 Y-tile width or the multiple of 16 Y-tile widths. The CCS surface pitch must be rounded up to power-of-two. Adjust the modifier descriptions accordingly. Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> --- include/uapi/drm/drm_fourcc.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 45a914850be0d..b63b7fa8bbac6 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -522,8 +522,16 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. + * line pair. + * + * The pitch of the main surface is required to be either 8 or a multiple of + * 16 Y-tile widths on Alderlake-P and a multiple of 4 Y-tile widths on other + * platforms. + * + * The pitch of the CCS surface must be calculated using the + * ccs_surface_pitch=main_surface_pitch_in_bytes / 512 * 64. + * formula. On Alderlake-P this pitch must be rounded up to be power-of-two + * sized. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) @@ -533,10 +541,12 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * line pair. For semi-planar formats like NV12, CCS planes follow the * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, * planes 2 and 3 for the respective CCS. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) @@ -554,8 +564,10 @@ extern "C" { * Clear Color value when applicable. The Converted Clear Color values are * consumed by the DE. The last 64 bits are used to store Color Discard Enable * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line - * corresponds to an area of 4x1 tiles in the main surface. The main surface - * pitch is required to be a multiple of 4 tile widths. + * corresponds to an area of 4x1 tiles in the main surface. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Imre Deak <imre.deak@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Nanley G Chery <nanley.g.chery@intel.com>, Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 6/6] drm/fourcc: Add the ADL-P specific pitch requirements of CCS modifiers Date: Mon, 6 Sep 2021 21:27:15 +0300 [thread overview] Message-ID: <20210906182715.3915100-7-imre.deak@intel.com> (raw) In-Reply-To: <20210906182715.3915100-1-imre.deak@intel.com> On Alderlake-P for all CCS modifiers the main surface pitch must be either 8 Y-tile width or the multiple of 16 Y-tile widths. The CCS surface pitch must be rounded up to power-of-two. Adjust the modifier descriptions accordingly. Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> --- include/uapi/drm/drm_fourcc.h | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 45a914850be0d..b63b7fa8bbac6 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -522,8 +522,16 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. + * line pair. + * + * The pitch of the main surface is required to be either 8 or a multiple of + * 16 Y-tile widths on Alderlake-P and a multiple of 4 Y-tile widths on other + * platforms. + * + * The pitch of the CCS surface must be calculated using the + * ccs_surface_pitch=main_surface_pitch_in_bytes / 512 * 64. + * formula. On Alderlake-P this pitch must be rounded up to be power-of-two + * sized. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) @@ -533,10 +541,12 @@ extern "C" { * The main surface is Y-tiled and at plane index 0, the CCS is linear and * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in * main surface. In other words, 4 bits in CCS map to a main surface cache - * line pair. The main surface pitch is required to be a multiple of four - * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the + * line pair. For semi-planar formats like NV12, CCS planes follow the * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, * planes 2 and 3 for the respective CCS. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) @@ -554,8 +564,10 @@ extern "C" { * Clear Color value when applicable. The Converted Clear Color values are * consumed by the DE. The last 64 bits are used to store Color Discard Enable * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line - * corresponds to an area of 4x1 tiles in the main surface. The main surface - * pitch is required to be a multiple of 4 tile widths. + * corresponds to an area of 4x1 tiles in the main surface. + * + * About the requirement on the main and CCS surface pitches see the + * description for I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS. */ #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) -- 2.27.0
next prev parent reply other threads:[~2021-09-06 18:27 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-06 18:27 [Intel-gfx] [PATCH v2 0/6] drm/i915/adlp: Add support for remapping CCS FBs Imre Deak 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 1/6] drm/i915: Use tile block based dimensions for CCS origin x, y check Imre Deak 2021-09-07 3:24 ` [Intel-gfx] [CI " Imre Deak 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/adlp: Require always a power-of-two sized CCS surface stride Imre Deak 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/adlp: Assert that VMAs in DPT start at 0 Imre Deak 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 4/6] drm/i915: Follow a new->old platform check order in intel_fb_stride_alignment Imre Deak 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 5/6] drm/i915/adlp: Add support for remapping CCS FBs Imre Deak 2021-09-06 18:27 ` Imre Deak [this message] 2021-09-06 18:27 ` [Intel-gfx] [PATCH v2 6/6] drm/fourcc: Add the ADL-P specific pitch requirements of CCS modifiers Imre Deak 2021-09-06 19:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Add support for remapping CCS FBs (rev2) Patchwork 2021-09-06 21:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-07 2:49 ` [Intel-gfx] [CI 0/6] drm/i915/adlp: Add support for remapping CCS FBs Imre Deak 2021-09-07 3:24 ` Imre Deak 2021-09-07 4:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Add support for remapping CCS FBs (rev3) Patchwork 2021-09-07 5:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-09-07 10:41 ` Imre Deak 2021-09-07 10:56 ` Sarvela, Tomi P 2021-09-23 15:15 ` Imre Deak
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