All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dave Airlie <airlied@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com, Dave Airlie <airlied@redhat.com>,
	Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable
Date: Thu,  9 Sep 2021 11:53:22 +1000	[thread overview]
Message-ID: <20210909015322.2988500-24-airlied@gmail.com> (raw)
In-Reply-To: <20210909015322.2988500-1-airlied@gmail.com>

From: Dave Airlie <airlied@redhat.com>

Use a nop table for the cases where CxSR doesn't init properly.

v2: use a nop table (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 34 ++++-----
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 drivers/gpu/drm/i915/intel_pm.c              | 80 ++++++++++++++------
 3 files changed, 75 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8b9727d84435..502e9ac70de1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
  */
 static void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-	if (dev_priv->wm_disp.update_wm)
-		dev_priv->wm_disp.update_wm(dev_priv);
+	if (dev_priv->wm_disp->update_wm)
+		dev_priv->wm_disp->update_wm(dev_priv);
 }
 
 static int intel_compute_pipe_wm(struct intel_atomic_state *state,
 				 struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	if (dev_priv->wm_disp.compute_pipe_wm)
-		return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+	if (dev_priv->wm_disp->compute_pipe_wm)
+		return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
 	return 0;
 }
 
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	if (drm_WARN_ON(&dev_priv->drm,
-			!dev_priv->wm_disp.compute_pipe_wm))
+			!dev_priv->wm_disp->compute_pipe_wm))
 		return 0;
-	if (dev_priv->wm_disp.compute_pipe_wm)
-		return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+	if (dev_priv->wm_disp->compute_pipe_wm)
+		return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
 	return 0;
 }
 
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct intel_atomic_state *state,
 				     struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	if (dev_priv->wm_disp.initial_watermarks) {
-		dev_priv->wm_disp.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp->initial_watermarks) {
+		dev_priv->wm_disp->initial_watermarks(state, crtc);
 		return true;
 	}
 	return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
 					   struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	if (dev_priv->wm_disp.atomic_update_watermarks)
-		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+	if (dev_priv->wm_disp->atomic_update_watermarks)
+		dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
 }
 
 static void intel_optimize_watermarks(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	if (dev_priv->wm_disp.optimize_watermarks)
-		dev_priv->wm_disp.optimize_watermarks(state, crtc);
+	if (dev_priv->wm_disp->optimize_watermarks)
+		dev_priv->wm_disp->optimize_watermarks(state, crtc);
 }
 
 static void intel_compute_global_watermarks(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-	if (dev_priv->wm_disp.compute_global_watermarks)
-		dev_priv->wm_disp.compute_global_watermarks(state);
+	if (dev_priv->wm_disp->compute_global_watermarks)
+		dev_priv->wm_disp->compute_global_watermarks(state);
 }
 
 /* returns HPLL frequency in kHz */
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(dev_priv) != 2)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (!dev_priv->wm_disp.initial_watermarks)
+	if (!dev_priv->wm_disp->initial_watermarks)
 		intel_update_watermarks(dev_priv);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11409,7 +11409,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
 	int i;
 
 	/* Only supported on platforms that use atomic watermark design */
-	if (!dev_priv->wm_disp.optimize_watermarks)
+	if (!dev_priv->wm_disp->optimize_watermarks)
 		return;
 
 	state = drm_atomic_state_alloc(&dev_priv->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc7466bbc445..b9fa6bf4835d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -978,7 +978,7 @@ struct drm_i915_private {
 	const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
 
 	/* pm display functions */
-	struct drm_i915_wm_disp_funcs wm_disp;
+	const struct drm_i915_wm_disp_funcs *wm_disp;
 
 	/* irq display functions */
 	const struct intel_hotplug_funcs *hotplug_funcs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0a5c1e3c798b..6f9e53a8dda2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7977,6 +7977,51 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 	}
 }
 
+static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
+	.compute_global_watermarks = skl_compute_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
+	.compute_pipe_wm = ilk_compute_pipe_wm,
+	.compute_intermediate_wm = ilk_compute_intermediate_wm,
+	.initial_watermarks = ilk_initial_watermarks,
+	.optimize_watermarks = ilk_optimize_watermarks,
+};
+
+static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
+	.compute_pipe_wm = vlv_compute_pipe_wm,
+	.compute_intermediate_wm = vlv_compute_intermediate_wm,
+	.initial_watermarks = vlv_initial_watermarks,
+	.optimize_watermarks = vlv_optimize_watermarks,
+	.atomic_update_watermarks = vlv_atomic_update_fifo,
+};
+
+static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
+	.compute_pipe_wm = g4x_compute_pipe_wm,
+	.compute_intermediate_wm = g4x_compute_intermediate_wm,
+	.initial_watermarks = g4x_initial_watermarks,
+	.optimize_watermarks = g4x_optimize_watermarks,
+};
+
+static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
+	.update_wm = pnv_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
+	.update_wm = i965_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
+	.update_wm = i9xx_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
+	.update_wm = i845_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs nop_funcs = {
+};
+
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_i915_private *dev_priv)
 {
@@ -7992,7 +8037,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	/* For FIFO watermark updates */
 	if (DISPLAY_VER(dev_priv) >= 9) {
 		skl_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
+		dev_priv->wm_disp = &skl_wm_funcs;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_setup_wm_latency(dev_priv);
 
@@ -8000,31 +8045,19 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
 		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
 		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
-			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
-			dev_priv->wm_disp.compute_intermediate_wm =
-				ilk_compute_intermediate_wm;
-			dev_priv->wm_disp.initial_watermarks =
-				ilk_initial_watermarks;
-			dev_priv->wm_disp.optimize_watermarks =
-				ilk_optimize_watermarks;
+			dev_priv->wm_disp = &ilk_wm_funcs;
 		} else {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Failed to read display plane latency. "
 				    "Disable CxSR\n");
+			dev_priv->wm_disp = &nop_funcs;
 		}
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
-		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
-		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
-		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
-		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
+		dev_priv->wm_disp = &vlv_wm_funcs;
 	} else if (IS_G4X(dev_priv)) {
 		g4x_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
-		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
-		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
-		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
+		dev_priv->wm_disp = &g4x_wm_funcs;
 	} else if (IS_PINEVIEW(dev_priv)) {
 		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 					    dev_priv->is_ddr3,
@@ -8038,21 +8071,22 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
-			dev_priv->wm_disp.update_wm = NULL;
+			dev_priv->wm_disp = &nop_funcs;
 		} else
-			dev_priv->wm_disp.update_wm = pnv_update_wm;
+			dev_priv->wm_disp = &pnv_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 4) {
-		dev_priv->wm_disp.update_wm = i965_update_wm;
+		dev_priv->wm_disp = &i965_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 3) {
-		dev_priv->wm_disp.update_wm = i9xx_update_wm;
+		dev_priv->wm_disp = &i9xx_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 2) {
 		if (INTEL_NUM_PIPES(dev_priv) == 1)
-			dev_priv->wm_disp.update_wm = i845_update_wm;
+			dev_priv->wm_disp = &i845_wm_funcs;
 		else
-			dev_priv->wm_disp.update_wm = i9xx_update_wm;
+			dev_priv->wm_disp = &i9xx_wm_funcs;
 	} else {
 		drm_err(&dev_priv->drm,
 			"unexpected fall-through in %s\n", __func__);
+		dev_priv->wm_disp = &nop_funcs;
 	}
 }
 
-- 
2.31.1


  parent reply	other threads:[~2021-09-09  1:54 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-09  1:52 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v3) Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 01/23] drm/i915/pm: drop get_fifo_size vfunc Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 02/23] drm/i915: make update_wm take a dev_priv Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 03/23] drm/i915/wm: provide wrappers around watermark vfuncs calls Dave Airlie
2021-09-09  8:48   ` Jani Nikula
2021-09-09  1:53 ` [Intel-gfx] [PATCH 04/23] drm/i915: add wrappers around cdclk vtable funcs Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 05/23] drm/i915/display: add intel_fdi_link_train wrapper Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 08/23] drm/i915: split color functions " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 09/23] drm/i915: split audio " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 10/23] drm/i915: split cdclk " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 16/23] drm/i915: constify color " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 17/23] drm/i915: constify the audio " Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable Dave Airlie
2021-09-09  1:53 ` [Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable Dave Airlie
2021-09-09  1:53 ` Dave Airlie [this message]
2021-09-09  2:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable (rev3) Patchwork
2021-09-09  2:13 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-09-09  2:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-09  7:17 ` [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v3) Saarinen, Jani
  -- strict thread matches above, loose matches on Subject: below --
2021-09-09  1:10 [Intel-gfx] [PATCH 00/23] i915/display: split and constify vtable (v2) Dave Airlie
2021-09-09  1:11 ` [Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable Dave Airlie

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210909015322.2988500-24-airlied@gmail.com \
    --to=airlied@gmail.com \
    --cc=airlied@redhat.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=jani.nikula@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.