From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Date: Tue, 12 Oct 2021 02:16:15 +0530 [thread overview] Message-ID: <20211011204619.81893-11-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> Manufacturers like Gigadevice and Winbond are adding Power-on-Reset functionality in their SPI NAND flash chips. PoR instruction consists of a 66h command followed by 99h command, and is different from the FFh reset. The reset command FFh just clears the status only registers, while the PoR command erases all the configurations written to the flash and is equivalent to a power-down -> power-up cycle. Add support for the Power-on-Reset command for any flash that provides this feature. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 43 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 17 +++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 2bea21bd9747..9b570570ee81 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "spi-nand: " fmt +#include <linux/delay.h> #include <linux/device.h> #include <linux/jiffies.h> #include <linux/kernel.h> @@ -668,6 +669,48 @@ static int spinand_reset_op(struct spinand_device *spinand) NULL); } +static int spinand_power_on_rst_op(struct spinand_device *spinand) +{ + struct spi_mem_op op; + int ret; + + if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT)) + return -EOPNOTSUPP; + + /* + * If flash is in a busy state, wait for it to finish the operation. + * As the operation is unknown, use reset poll delays here. + */ + ret = spinand_wait(spinand, + SPINAND_RESET_INITIAL_DELAY_US, + SPINAND_RESET_POLL_DELAY_US, + NULL); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_EN_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + /* PoR can take max 500 us to complete, so sleep for 600 to 700 us*/ + usleep_range(SPINAND_POR_MIN_DELAY_US, SPINAND_POR_MAX_DELAY_US); + + dev_dbg(&spinand->spimem->spi->dev, + "%s SPI NAND reset to Power-On-Reset state.\n", + spinand->manufacturer->name); + return 0; +} + static int spinand_lock_block(struct spinand_device *spinand, u8 lock) { return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 21a4e5adcd59..baaf8e94f301 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -26,6 +26,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +#define SPINAND_EN_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x66, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x99, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + #define SPINAND_WR_EN_DIS_OP(enable) \ SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -218,6 +230,8 @@ struct spinand_device; * reading/programming/erasing when the RESET occurs. Since we always * issue a RESET when the device is IDLE, 5us is selected for both initial * and poll delay. + * Power on Reset can take upto 500 us to complete, so sleep for 600 us + * to 700 us safely. */ #define SPINAND_READ_INITIAL_DELAY_US 6 #define SPINAND_READ_POLL_DELAY_US 5 @@ -227,6 +241,8 @@ struct spinand_device; #define SPINAND_WRITE_POLL_DELAY_US 15 #define SPINAND_ERASE_INITIAL_DELAY_US 250 #define SPINAND_ERASE_POLL_DELAY_US 50 +#define SPINAND_POR_MIN_DELAY_US 600 +#define SPINAND_POR_MAX_DELAY_US 700 #define SPINAND_WAITRDY_TIMEOUT_MS 400 @@ -351,6 +367,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) #define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) +#define SPINAND_HAS_POR_CMD_BIT BIT(3) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Apurva Nandan <a-nandan@ti.com> To: Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>, Patrice Chotard <patrice.chotard@foss.st.com>, Christophe Kerello <christophe.kerello@foss.st.com>, Boris Brezillon <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org> Cc: <p.yadav@ti.com> Subject: [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Date: Tue, 12 Oct 2021 02:16:15 +0530 [thread overview] Message-ID: <20211011204619.81893-11-a-nandan@ti.com> (raw) In-Reply-To: <20211011204619.81893-1-a-nandan@ti.com> Manufacturers like Gigadevice and Winbond are adding Power-on-Reset functionality in their SPI NAND flash chips. PoR instruction consists of a 66h command followed by 99h command, and is different from the FFh reset. The reset command FFh just clears the status only registers, while the PoR command erases all the configurations written to the flash and is equivalent to a power-down -> power-up cycle. Add support for the Power-on-Reset command for any flash that provides this feature. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan <a-nandan@ti.com> --- drivers/mtd/nand/spi/core.c | 43 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 17 +++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 2bea21bd9747..9b570570ee81 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "spi-nand: " fmt +#include <linux/delay.h> #include <linux/device.h> #include <linux/jiffies.h> #include <linux/kernel.h> @@ -668,6 +669,48 @@ static int spinand_reset_op(struct spinand_device *spinand) NULL); } +static int spinand_power_on_rst_op(struct spinand_device *spinand) +{ + struct spi_mem_op op; + int ret; + + if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT)) + return -EOPNOTSUPP; + + /* + * If flash is in a busy state, wait for it to finish the operation. + * As the operation is unknown, use reset poll delays here. + */ + ret = spinand_wait(spinand, + SPINAND_RESET_INITIAL_DELAY_US, + SPINAND_RESET_POLL_DELAY_US, + NULL); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_EN_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + op = (struct spi_mem_op)SPINAND_POWER_ON_RST_OP; + + spinand_patch_op(spinand, &op); + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + /* PoR can take max 500 us to complete, so sleep for 600 to 700 us*/ + usleep_range(SPINAND_POR_MIN_DELAY_US, SPINAND_POR_MAX_DELAY_US); + + dev_dbg(&spinand->spimem->spi->dev, + "%s SPI NAND reset to Power-On-Reset state.\n", + spinand->manufacturer->name); + return 0; +} + static int spinand_lock_block(struct spinand_device *spinand, u8 lock) { return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 21a4e5adcd59..baaf8e94f301 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -26,6 +26,18 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +#define SPINAND_EN_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x66, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + +#define SPINAND_POWER_ON_RST_OP \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x99, 1), \ + SPI_MEM_OP_NO_ADDR, \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_NO_DATA) + #define SPINAND_WR_EN_DIS_OP(enable) \ SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \ SPI_MEM_OP_NO_ADDR, \ @@ -218,6 +230,8 @@ struct spinand_device; * reading/programming/erasing when the RESET occurs. Since we always * issue a RESET when the device is IDLE, 5us is selected for both initial * and poll delay. + * Power on Reset can take upto 500 us to complete, so sleep for 600 us + * to 700 us safely. */ #define SPINAND_READ_INITIAL_DELAY_US 6 #define SPINAND_READ_POLL_DELAY_US 5 @@ -227,6 +241,8 @@ struct spinand_device; #define SPINAND_WRITE_POLL_DELAY_US 15 #define SPINAND_ERASE_INITIAL_DELAY_US 250 #define SPINAND_ERASE_POLL_DELAY_US 50 +#define SPINAND_POR_MIN_DELAY_US 600 +#define SPINAND_POR_MAX_DELAY_US 700 #define SPINAND_WAITRDY_TIMEOUT_MS 400 @@ -351,6 +367,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_QE_BIT BIT(0) #define SPINAND_HAS_CR_FEAT_BIT BIT(1) #define SPINAND_HAS_OCTAL_DTR_BIT BIT(2) +#define SPINAND_HAS_POR_CMD_BIT BIT(3) /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-10-11 20:47 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-11 20:46 [PATCH v2 00/14] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 01/14] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 02/14] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:39 ` Boris Brezillon 2021-10-12 6:39 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 03/14] mtd: spinand: Patch spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:40 ` Boris Brezillon 2021-10-12 6:40 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 04/14] mtd: spinand: Fix odd byte addr and data phase in read and write reg op for Octal DTR mode Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 05/14] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 6:54 ` Boris Brezillon 2021-10-12 6:54 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 06/14] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 07/14] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:14 ` Boris Brezillon 2021-10-12 7:14 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 08/14] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 09/14] mtd: spinand: winbond: Add octal_dtr_enable() for manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan [this message] 2021-10-11 20:46 ` [PATCH v2 10/14] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 11/14] mtd: spinand: Perform Power-on-Reset on the flash in mtd_suspend() Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-12 7:25 ` Boris Brezillon 2021-10-12 7:25 ` Boris Brezillon 2021-10-11 20:46 ` [PATCH v2 12/14] mtd: spinand: Add adjust_op() in Winbond manufacturer_ops Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 13/14] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan 2021-10-11 20:46 ` [PATCH v2 14/14] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan 2021-10-11 20:46 ` Apurva Nandan
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