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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: <john.c.harrison@intel.com>
Subject: [Intel-gfx] [PATCH 09/25] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts
Date: Wed, 13 Oct 2021 13:42:15 -0700	[thread overview]
Message-ID: <20211013204231.19287-10-matthew.brost@intel.com> (raw)
In-Reply-To: <20211013204231.19287-1-matthew.brost@intel.com>

In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 58a6f494be8f..abf867f4f659 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -324,6 +324,12 @@ static inline void decr_context_committed_requests(struct intel_context *ce)
 	GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
 }
 
+static struct intel_context *
+request_to_scheduling_context(struct i915_request *rq)
+{
+	return intel_context_to_parent(rq->context);
+}
+
 static inline bool context_guc_id_invalid(struct intel_context *ce)
 {
 	return ce->guc_id.id == GUC_INVALID_LRC_ID;
@@ -1712,6 +1718,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
 
 	GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
 
+	GEM_BUG_ON(intel_context_is_child(ce));
 	trace_intel_context_sched_disable(ce);
 
 	guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
@@ -1937,6 +1944,8 @@ static void guc_context_sched_disable(struct intel_context *ce)
 	intel_wakeref_t wakeref;
 	u16 guc_id;
 
+	GEM_BUG_ON(intel_context_is_child(ce));
+
 	spin_lock_irqsave(&ce->guc_state.lock, flags);
 
 	/*
@@ -2305,6 +2314,8 @@ static void guc_signal_context_fence(struct intel_context *ce)
 {
 	unsigned long flags;
 
+	GEM_BUG_ON(intel_context_is_child(ce));
+
 	spin_lock_irqsave(&ce->guc_state.lock, flags);
 	clr_context_wait_for_deregister_to_register(ce);
 	__guc_signal_context_fence(ce);
@@ -2335,7 +2346,7 @@ static void guc_context_init(struct intel_context *ce)
 
 static int guc_request_alloc(struct i915_request *rq)
 {
-	struct intel_context *ce = rq->context;
+	struct intel_context *ce = request_to_scheduling_context(rq);
 	struct intel_guc *guc = ce_to_guc(ce);
 	unsigned long flags;
 	int ret;
-- 
2.32.0


WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: <john.c.harrison@intel.com>
Subject: [PATCH 09/25] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts
Date: Wed, 13 Oct 2021 13:42:15 -0700	[thread overview]
Message-ID: <20211013204231.19287-10-matthew.brost@intel.com> (raw)
In-Reply-To: <20211013204231.19287-1-matthew.brost@intel.com>

In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 58a6f494be8f..abf867f4f659 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -324,6 +324,12 @@ static inline void decr_context_committed_requests(struct intel_context *ce)
 	GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
 }
 
+static struct intel_context *
+request_to_scheduling_context(struct i915_request *rq)
+{
+	return intel_context_to_parent(rq->context);
+}
+
 static inline bool context_guc_id_invalid(struct intel_context *ce)
 {
 	return ce->guc_id.id == GUC_INVALID_LRC_ID;
@@ -1712,6 +1718,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
 
 	GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
 
+	GEM_BUG_ON(intel_context_is_child(ce));
 	trace_intel_context_sched_disable(ce);
 
 	guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
@@ -1937,6 +1944,8 @@ static void guc_context_sched_disable(struct intel_context *ce)
 	intel_wakeref_t wakeref;
 	u16 guc_id;
 
+	GEM_BUG_ON(intel_context_is_child(ce));
+
 	spin_lock_irqsave(&ce->guc_state.lock, flags);
 
 	/*
@@ -2305,6 +2314,8 @@ static void guc_signal_context_fence(struct intel_context *ce)
 {
 	unsigned long flags;
 
+	GEM_BUG_ON(intel_context_is_child(ce));
+
 	spin_lock_irqsave(&ce->guc_state.lock, flags);
 	clr_context_wait_for_deregister_to_register(ce);
 	__guc_signal_context_fence(ce);
@@ -2335,7 +2346,7 @@ static void guc_context_init(struct intel_context *ce)
 
 static int guc_request_alloc(struct i915_request *rq)
 {
-	struct intel_context *ce = rq->context;
+	struct intel_context *ce = request_to_scheduling_context(rq);
 	struct intel_guc *guc = ce_to_guc(ce);
 	unsigned long flags;
 	int ret;
-- 
2.32.0


  parent reply	other threads:[~2021-10-13 20:56 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-13 20:42 [PATCH 00/25] Parallel submission aka multi-bb execbuf Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 01/25] drm/i915/guc: Move GuC guc_id allocation under submission state sub-struct Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 23:56   ` John Harrison
2021-10-13 23:56     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 02/25] drm/i915/guc: Take GT PM ref when deregistering context Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 23:59   ` John Harrison
2021-10-13 23:59     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 03/25] drm/i915/guc: Take engine PM when a context is pinned with GuC submission Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:05   ` John Harrison
2021-10-14  0:05     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 04/25] drm/i915/guc: Don't call switch_to_kernel_context " Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 05/25] drm/i915: Add logical engine mapping Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 06/25] drm/i915: Expose logical engine instance to user Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 07/25] drm/i915/guc: Introduce context parent-child relationship Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 20:42 ` [PATCH 08/25] drm/i915/guc: Add multi-lrc context registration Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:10   ` John Harrison
2021-10-14  0:10     ` [Intel-gfx] " John Harrison
2021-10-14  4:26     ` Matthew Brost
2021-10-14  4:26       ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` Matthew Brost [this message]
2021-10-13 20:42   ` [PATCH 09/25] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost
2021-10-13 20:42 ` [PATCH 10/25] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 11/25] drm/i915/guc: Implement parallel context pin / unpin functions Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14 16:56   ` John Harrison
2021-10-14 16:56     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 12/25] drm/i915/guc: Implement multi-lrc submission Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:25   ` John Harrison
2021-10-14  0:25     ` John Harrison
2021-10-13 20:42 ` [PATCH 13/25] drm/i915/guc: Insert submit fences between requests in parent-child relationship Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 14/25] drm/i915/guc: Implement multi-lrc reset Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:28   ` John Harrison
2021-10-14  0:28     ` [Intel-gfx] " John Harrison
2021-10-14 16:26   ` kernel test robot
2021-10-14 16:26     ` kernel test robot
2021-10-14 16:26     ` [Intel-gfx] " kernel test robot
2021-10-13 20:42 ` [Intel-gfx] [PATCH 15/25] drm/i915/guc: Update debugfs for GuC multi-lrc Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 20:42 ` [PATCH 16/25] drm/i915/guc: Connect UAPI to GuC multi-lrc interface Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  1:02   ` John Harrison
2021-10-14  1:02     ` [Intel-gfx] " John Harrison
2021-10-14 15:32     ` Matthew Brost
2021-10-14 15:32       ` [Intel-gfx] " Matthew Brost
2021-10-14 16:43       ` John Harrison
2021-10-14 16:43         ` [Intel-gfx] " John Harrison
2021-10-14 16:41         ` Matthew Brost
2021-10-14 16:41           ` Matthew Brost
2021-10-14 17:15           ` John Harrison
2021-10-14 17:15             ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 17/25] drm/i915/doc: Update parallel submit doc to point to i915_drm.h Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 18/25] drm/i915/guc: Add basic GuC multi-lrc selftest Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [Intel-gfx] [PATCH 19/25] drm/i915/guc: Implement no mid batch preemption for multi-lrc Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-14  0:48   ` John Harrison
2021-10-14  0:48     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [Intel-gfx] [PATCH 20/25] drm/i915: Multi-BB execbuf Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-14  0:55   ` John Harrison
2021-10-14  0:55     ` [Intel-gfx] " John Harrison
2021-10-14 15:34     ` Matthew Brost
2021-10-14 15:34       ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 21/25] drm/i915/guc: Handle errors in multi-lrc requests Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:57   ` John Harrison
2021-10-14  0:57     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [PATCH 22/25] drm/i915: Make request conflict tracking understand parallel submits Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-14  0:59   ` John Harrison
2021-10-14  0:59     ` [Intel-gfx] " John Harrison
2021-10-13 20:42 ` [Intel-gfx] [PATCH 23/25] drm/i915: Update I915_GEM_BUSY IOCTL to understand composite fences Matthew Brost
2021-10-13 20:42   ` Matthew Brost
2021-10-13 20:42 ` [PATCH 24/25] drm/i915: Enable multi-bb execbuf Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 20:42 ` [PATCH 25/25] drm/i915/execlists: Weak parallel submission support for execlists Matthew Brost
2021-10-13 20:42   ` [Intel-gfx] " Matthew Brost
2021-10-13 21:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev6) Patchwork
2021-10-13 21:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-13 22:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-14 17:19 [PATCH 00/25] Parallel submission aka multi-bb execbuf Matthew Brost
2021-10-14 17:19 ` [Intel-gfx] [PATCH 09/25] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts Matthew Brost

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