From: <conor.dooley@microchip.com> To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>, <robh+dt@kernel.org>, <jassisinghbrar@gmail.com>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <broonie@kernel.org>, <gregkh@linuxfoundation.org>, <lewis.hanly@microchip.com>, <conor.dooley@microchip.com>, <daire.mcnamara@microchip.com>, <atish.patra@wdc.com>, <ivan.griffin@microchip.com>, <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org> Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>, <bin.meng@windriver.com> Subject: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Mon, 8 Nov 2021 15:05:50 +0000 [thread overview] Message-ID: <20211108150554.4457-10-conor.dooley@microchip.com> (raw) In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> From: Conor Dooley <conor.dooley@microchip.com> Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..067019ddc1f7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + This GPIO controller is found on the Microchip PolarFire SoC. + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + - microsemi,ms-pf-mss-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" + soc { + #address-cells = <2>; + #size-cells = <2>; + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + interrupts = <PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +... -- 2.33.1
WARNING: multiple messages have this Message-ID (diff)
From: <conor.dooley@microchip.com> To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>, <robh+dt@kernel.org>, <jassisinghbrar@gmail.com>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <broonie@kernel.org>, <gregkh@linuxfoundation.org>, <lewis.hanly@microchip.com>, <conor.dooley@microchip.com>, <daire.mcnamara@microchip.com>, <atish.patra@wdc.com>, <ivan.griffin@microchip.com>, <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org> Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>, <bin.meng@windriver.com> Subject: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Mon, 8 Nov 2021 15:05:50 +0000 [thread overview] Message-ID: <20211108150554.4457-10-conor.dooley@microchip.com> (raw) In-Reply-To: <20211108150554.4457-1-conor.dooley@microchip.com> From: Conor Dooley <conor.dooley@microchip.com> Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..067019ddc1f7 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + This GPIO controller is found on the Microchip PolarFire SoC. + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + - microsemi,ms-pf-mss-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h" + soc { + #address-cells = <2>; + #size-cells = <2>; + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + interrupts = <PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT + PLIC_INT_GPIO2_NON_DIRECT>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +... -- 2.33.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-11-08 15:08 UTC|newest] Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-08 15:05 [PATCH 00/13]Update the icicle kit device tree conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 15:05 ` [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-23 11:07 ` Heiko Stübner 2021-11-23 11:07 ` Heiko Stübner 2021-11-23 11:35 ` Anup Patel 2021-11-23 11:35 ` Anup Patel 2021-11-29 19:57 ` Rob Herring 2021-11-29 19:57 ` Rob Herring 2021-11-08 15:05 ` [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-23 11:17 ` Heiko Stübner 2021-11-23 11:17 ` Heiko Stübner 2021-11-29 19:56 ` Rob Herring 2021-11-29 19:56 ` Rob Herring 2021-11-30 8:15 ` Conor.Dooley 2021-11-30 8:15 ` Conor.Dooley 2021-11-08 15:05 ` [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:09 ` Krzysztof Kozlowski 2021-11-08 21:09 ` Krzysztof Kozlowski 2021-11-09 8:33 ` Geert Uytterhoeven 2021-11-09 8:33 ` Geert Uytterhoeven 2021-11-09 15:20 ` Conor.Dooley 2021-11-09 15:20 ` Conor.Dooley 2021-11-29 20:03 ` Rob Herring 2021-11-29 20:03 ` Rob Herring 2021-11-30 8:35 ` Conor.Dooley 2021-11-30 8:35 ` Conor.Dooley 2021-11-08 15:05 ` [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:10 ` Krzysztof Kozlowski 2021-11-08 21:10 ` Krzysztof Kozlowski 2021-11-09 8:34 ` Geert Uytterhoeven 2021-11-09 8:34 ` Geert Uytterhoeven 2021-11-09 12:08 ` Conor.Dooley 2021-11-09 12:08 ` Conor.Dooley 2021-11-09 13:04 ` Geert Uytterhoeven 2021-11-09 13:04 ` Geert Uytterhoeven 2021-11-23 11:24 ` Heiko Stübner 2021-11-23 11:24 ` Heiko Stübner 2021-11-08 15:05 ` [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:13 ` Krzysztof Kozlowski 2021-11-08 21:13 ` Krzysztof Kozlowski 2021-11-09 4:06 ` Rob Herring 2021-11-09 4:06 ` Rob Herring 2021-11-08 15:05 ` [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:16 ` Krzysztof Kozlowski 2021-11-08 21:16 ` Krzysztof Kozlowski 2021-11-09 12:54 ` Conor.Dooley 2021-11-09 12:54 ` Conor.Dooley 2021-11-09 12:56 ` Krzysztof Kozlowski 2021-11-09 12:56 ` Krzysztof Kozlowski 2021-11-09 13:36 ` Conor.Dooley 2021-11-09 13:36 ` Conor.Dooley 2021-11-10 7:43 ` Krzysztof Kozlowski 2021-11-10 7:43 ` Krzysztof Kozlowski 2021-11-10 9:46 ` Conor.Dooley 2021-11-10 9:46 ` Conor.Dooley 2021-11-29 20:08 ` Rob Herring 2021-11-29 20:08 ` Rob Herring 2021-11-09 8:37 ` Geert Uytterhoeven 2021-11-09 8:37 ` Geert Uytterhoeven 2021-11-09 11:55 ` Conor.Dooley 2021-11-09 11:55 ` Conor.Dooley 2021-11-08 15:05 ` [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:20 ` Krzysztof Kozlowski 2021-11-08 21:20 ` Krzysztof Kozlowski 2021-11-09 4:06 ` Rob Herring 2021-11-09 4:06 ` Rob Herring 2021-11-09 8:39 ` Geert Uytterhoeven 2021-11-09 8:39 ` Geert Uytterhoeven 2021-11-08 15:05 ` [PATCH 08/13] dt-bindings: soc/microchip: add bindings for mpfs system services conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:20 ` Krzysztof Kozlowski 2021-11-08 21:20 ` Krzysztof Kozlowski 2021-11-08 15:05 ` conor.dooley [this message] 2021-11-08 15:05 ` [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley 2021-11-08 21:22 ` Krzysztof Kozlowski 2021-11-08 21:22 ` Krzysztof Kozlowski 2021-11-09 4:06 ` Rob Herring 2021-11-09 4:06 ` Rob Herring 2021-11-09 8:43 ` Geert Uytterhoeven 2021-11-09 8:43 ` Geert Uytterhoeven 2021-11-08 15:05 ` [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:24 ` Krzysztof Kozlowski 2021-11-08 21:24 ` Krzysztof Kozlowski 2021-11-09 4:06 ` Rob Herring 2021-11-09 4:06 ` Rob Herring 2021-11-09 12:16 ` Conor.Dooley 2021-11-09 12:16 ` Conor.Dooley 2021-11-09 12:53 ` Krzysztof Kozlowski 2021-11-09 12:53 ` Krzysztof Kozlowski 2021-11-09 12:58 ` Conor.Dooley 2021-11-09 12:58 ` Conor.Dooley 2021-11-09 13:04 ` Krzysztof Kozlowski 2021-11-09 13:04 ` Krzysztof Kozlowski 2021-11-09 13:20 ` Conor.Dooley 2021-11-09 13:20 ` Conor.Dooley 2021-11-10 7:45 ` Krzysztof Kozlowski 2021-11-10 7:45 ` Krzysztof Kozlowski 2021-11-09 8:45 ` Geert Uytterhoeven 2021-11-09 8:45 ` Geert Uytterhoeven 2021-11-09 10:56 ` Conor.Dooley 2021-11-09 10:56 ` Conor.Dooley 2021-11-08 15:05 ` [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:27 ` Krzysztof Kozlowski 2021-11-08 21:27 ` Krzysztof Kozlowski 2021-11-09 4:06 ` Rob Herring 2021-11-09 4:06 ` Rob Herring 2021-11-09 8:48 ` Geert Uytterhoeven 2021-11-09 8:48 ` Geert Uytterhoeven 2021-11-08 15:05 ` [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree conor.dooley 2021-11-08 15:05 ` conor.dooley 2021-11-08 21:40 ` Krzysztof Kozlowski 2021-11-08 21:40 ` Krzysztof Kozlowski 2021-11-10 12:07 ` Conor.Dooley 2021-11-10 12:07 ` Conor.Dooley 2021-11-09 9:04 ` Geert Uytterhoeven 2021-11-09 9:04 ` Geert Uytterhoeven 2021-11-10 14:19 ` Conor.Dooley 2021-11-10 14:19 ` Conor.Dooley 2021-11-10 14:58 ` Geert Uytterhoeven 2021-11-10 14:58 ` Geert Uytterhoeven 2021-11-10 15:07 ` Conor.Dooley 2021-11-10 15:07 ` Conor.Dooley 2021-11-15 15:39 ` Conor.Dooley 2021-11-15 15:39 ` Conor.Dooley 2021-11-15 16:17 ` Geert Uytterhoeven 2021-11-15 16:17 ` Geert Uytterhoeven 2021-11-17 12:17 ` Daire.McNamara 2021-11-17 12:17 ` Daire.McNamara 2021-11-08 15:05 ` [PATCH 13/13] MAINTAINERS: update riscv/microchip entry conor.dooley 2021-11-08 15:05 ` conor.dooley
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