From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Björn Töpel" <bjorn@kernel.org>, "Alexei Starovoitov" <ast@kernel.org>, "Daniel Borkmann" <daniel@iogearbox.net>, "Andrii Nakryiko" <andrii@kernel.org>, "Martin KaFai Lau" <kafai@fb.com>, "Song Liu" <songliubraving@fb.com>, "Yonghong Song" <yhs@fb.com>, "John Fastabend" <john.fastabend@gmail.com>, "KP Singh" <kpsingh@kernel.org>, "Masahiro Yamada" <masahiroy@kernel.org>, "Michal Marek" <michal.lkml@markovi.net>, "Nick Desaulniers" <ndesaulniers@google.com> Cc: Kefeng Wang <wangkefeng.wang@huawei.com>, Tong Tiangen <tongtiangen@huawei.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-kbuild@vger.kernel.org Subject: [PATCH 10/12] riscv: add gpr-num.h Date: Thu, 18 Nov 2021 19:26:29 +0800 [thread overview] Message-ID: <20211118192629.0a9dc6ad@xhacker> (raw) In-Reply-To: <20211118192130.48b8f04c@xhacker> From: Jisheng Zhang <jszhang@kernel.org> Next patch will use the gpr-num to pass the register number to exception fixup handler which sits in inline assembly routines. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/gpr-num.h | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/riscv/include/asm/gpr-num.h diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h new file mode 100644 index 000000000000..dfee2829fc7c --- /dev/null +++ b/arch/riscv/include/asm/gpr-num.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_GPR_NUM_H +#define __ASM_GPR_NUM_H + +#ifdef __ASSEMBLY__ + .equ .L__gpr_num_zero, 0 + .equ .L__gpr_num_ra, 1 + .equ .L__gpr_num_sp, 2 + .equ .L__gpr_num_gp, 3 + .equ .L__gpr_num_tp, 4 + .equ .L__gpr_num_t0, 5 + .equ .L__gpr_num_t1, 6 + .equ .L__gpr_num_t2, 7 + .equ .L__gpr_num_s0, 8 + .equ .L__gpr_num_s1, 9 + .equ .L__gpr_num_a0, 10 + .equ .L__gpr_num_a1, 11 + .equ .L__gpr_num_a2, 12 + .equ .L__gpr_num_a3, 13 + .equ .L__gpr_num_a4, 14 + .equ .L__gpr_num_a5, 15 + .equ .L__gpr_num_a6, 16 + .equ .L__gpr_num_a7, 17 + .equ .L__gpr_num_s2, 18 + .equ .L__gpr_num_s3, 19 + .equ .L__gpr_num_s4, 20 + .equ .L__gpr_num_s5, 21 + .equ .L__gpr_num_s6, 22 + .equ .L__gpr_num_s7, 23 + .equ .L__gpr_num_s8, 24 + .equ .L__gpr_num_s9, 25 + .equ .L__gpr_num_s10, 26 + .equ .L__gpr_num_s11, 27 + .equ .L__gpr_num_t3, 28 + .equ .L__gpr_num_t4, 29 + .equ .L__gpr_num_t5, 30 + .equ .L__gpr_num_t6, 31 + +#else /* __ASSEMBLY__ */ + +#define __DEFINE_ASM_GPR_NUMS \ +" .equ .L__gpr_num_zero, 0\n" \ +" .equ .L__gpr_num_ra, 1\n" \ +" .equ .L__gpr_num_sp, 2\n" \ +" .equ .L__gpr_num_gp, 3\n" \ +" .equ .L__gpr_num_tp, 4\n" \ +" .equ .L__gpr_num_t0, 5\n" \ +" .equ .L__gpr_num_t1, 6\n" \ +" .equ .L__gpr_num_t2, 7\n" \ +" .equ .L__gpr_num_s0, 8\n" \ +" .equ .L__gpr_num_s1, 9\n" \ +" .equ .L__gpr_num_a0, 10\n" \ +" .equ .L__gpr_num_a1, 11\n" \ +" .equ .L__gpr_num_a2, 12\n" \ +" .equ .L__gpr_num_a3, 13\n" \ +" .equ .L__gpr_num_a4, 14\n" \ +" .equ .L__gpr_num_a5, 15\n" \ +" .equ .L__gpr_num_a6, 16\n" \ +" .equ .L__gpr_num_a7, 17\n" \ +" .equ .L__gpr_num_s2, 18\n" \ +" .equ .L__gpr_num_s3, 19\n" \ +" .equ .L__gpr_num_s4, 20\n" \ +" .equ .L__gpr_num_s5, 21\n" \ +" .equ .L__gpr_num_s6, 22\n" \ +" .equ .L__gpr_num_s7, 23\n" \ +" .equ .L__gpr_num_s8, 24\n" \ +" .equ .L__gpr_num_s9, 25\n" \ +" .equ .L__gpr_num_s10, 26\n" \ +" .equ .L__gpr_num_s11, 27\n" \ +" .equ .L__gpr_num_t3, 28\n" \ +" .equ .L__gpr_num_t4, 29\n" \ +" .equ .L__gpr_num_t5, 30\n" \ +" .equ .L__gpr_num_t6, 31\n" + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GPR_NUM_H */ -- 2.33.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn> To: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Björn Töpel" <bjorn@kernel.org>, "Alexei Starovoitov" <ast@kernel.org>, "Daniel Borkmann" <daniel@iogearbox.net>, "Andrii Nakryiko" <andrii@kernel.org>, "Martin KaFai Lau" <kafai@fb.com>, "Song Liu" <songliubraving@fb.com>, "Yonghong Song" <yhs@fb.com>, "John Fastabend" <john.fastabend@gmail.com>, "KP Singh" <kpsingh@kernel.org>, "Masahiro Yamada" <masahiroy@kernel.org>, "Michal Marek" <michal.lkml@markovi.net>, "Nick Desaulniers" <ndesaulniers@google.com> Cc: Kefeng Wang <wangkefeng.wang@huawei.com>, Tong Tiangen <tongtiangen@huawei.com>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-kbuild@vger.kernel.org Subject: [PATCH 10/12] riscv: add gpr-num.h Date: Thu, 18 Nov 2021 19:26:29 +0800 [thread overview] Message-ID: <20211118192629.0a9dc6ad@xhacker> (raw) In-Reply-To: <20211118192130.48b8f04c@xhacker> From: Jisheng Zhang <jszhang@kernel.org> Next patch will use the gpr-num to pass the register number to exception fixup handler which sits in inline assembly routines. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/include/asm/gpr-num.h | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 arch/riscv/include/asm/gpr-num.h diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h new file mode 100644 index 000000000000..dfee2829fc7c --- /dev/null +++ b/arch/riscv/include/asm/gpr-num.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_GPR_NUM_H +#define __ASM_GPR_NUM_H + +#ifdef __ASSEMBLY__ + .equ .L__gpr_num_zero, 0 + .equ .L__gpr_num_ra, 1 + .equ .L__gpr_num_sp, 2 + .equ .L__gpr_num_gp, 3 + .equ .L__gpr_num_tp, 4 + .equ .L__gpr_num_t0, 5 + .equ .L__gpr_num_t1, 6 + .equ .L__gpr_num_t2, 7 + .equ .L__gpr_num_s0, 8 + .equ .L__gpr_num_s1, 9 + .equ .L__gpr_num_a0, 10 + .equ .L__gpr_num_a1, 11 + .equ .L__gpr_num_a2, 12 + .equ .L__gpr_num_a3, 13 + .equ .L__gpr_num_a4, 14 + .equ .L__gpr_num_a5, 15 + .equ .L__gpr_num_a6, 16 + .equ .L__gpr_num_a7, 17 + .equ .L__gpr_num_s2, 18 + .equ .L__gpr_num_s3, 19 + .equ .L__gpr_num_s4, 20 + .equ .L__gpr_num_s5, 21 + .equ .L__gpr_num_s6, 22 + .equ .L__gpr_num_s7, 23 + .equ .L__gpr_num_s8, 24 + .equ .L__gpr_num_s9, 25 + .equ .L__gpr_num_s10, 26 + .equ .L__gpr_num_s11, 27 + .equ .L__gpr_num_t3, 28 + .equ .L__gpr_num_t4, 29 + .equ .L__gpr_num_t5, 30 + .equ .L__gpr_num_t6, 31 + +#else /* __ASSEMBLY__ */ + +#define __DEFINE_ASM_GPR_NUMS \ +" .equ .L__gpr_num_zero, 0\n" \ +" .equ .L__gpr_num_ra, 1\n" \ +" .equ .L__gpr_num_sp, 2\n" \ +" .equ .L__gpr_num_gp, 3\n" \ +" .equ .L__gpr_num_tp, 4\n" \ +" .equ .L__gpr_num_t0, 5\n" \ +" .equ .L__gpr_num_t1, 6\n" \ +" .equ .L__gpr_num_t2, 7\n" \ +" .equ .L__gpr_num_s0, 8\n" \ +" .equ .L__gpr_num_s1, 9\n" \ +" .equ .L__gpr_num_a0, 10\n" \ +" .equ .L__gpr_num_a1, 11\n" \ +" .equ .L__gpr_num_a2, 12\n" \ +" .equ .L__gpr_num_a3, 13\n" \ +" .equ .L__gpr_num_a4, 14\n" \ +" .equ .L__gpr_num_a5, 15\n" \ +" .equ .L__gpr_num_a6, 16\n" \ +" .equ .L__gpr_num_a7, 17\n" \ +" .equ .L__gpr_num_s2, 18\n" \ +" .equ .L__gpr_num_s3, 19\n" \ +" .equ .L__gpr_num_s4, 20\n" \ +" .equ .L__gpr_num_s5, 21\n" \ +" .equ .L__gpr_num_s6, 22\n" \ +" .equ .L__gpr_num_s7, 23\n" \ +" .equ .L__gpr_num_s8, 24\n" \ +" .equ .L__gpr_num_s9, 25\n" \ +" .equ .L__gpr_num_s10, 26\n" \ +" .equ .L__gpr_num_s11, 27\n" \ +" .equ .L__gpr_num_t3, 28\n" \ +" .equ .L__gpr_num_t4, 29\n" \ +" .equ .L__gpr_num_t5, 30\n" \ +" .equ .L__gpr_num_t6, 31\n" + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GPR_NUM_H */ -- 2.33.0
next prev parent reply other threads:[~2021-11-18 11:35 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-18 11:21 [PATCH v4 0/12] riscv: switch to relative extable and other improvements Jisheng Zhang 2021-11-18 11:21 ` Jisheng Zhang 2021-11-18 11:22 ` [PATCH 01/12] riscv: remove unused __cmpxchg_user() macro Jisheng Zhang 2021-11-18 11:22 ` Jisheng Zhang 2021-11-18 11:22 ` [PATCH 02/12] riscv: consolidate __ex_table construction Jisheng Zhang 2021-11-18 11:22 ` Jisheng Zhang 2021-11-18 11:22 ` [PATCH 03/12] riscv: switch to relative exception tables Jisheng Zhang 2021-11-18 11:22 ` Jisheng Zhang 2021-11-19 2:09 ` tongtiangen 2021-11-19 2:09 ` tongtiangen 2021-11-18 11:23 ` [PATCH 04/12] riscv: bpf: move rv_bpf_fixup_exception signature to extable.h Jisheng Zhang 2021-11-18 11:23 ` Jisheng Zhang 2021-11-18 11:24 ` [PATCH 05/12] riscv: extable: make fixup_exception() return bool Jisheng Zhang 2021-11-18 11:24 ` Jisheng Zhang 2021-11-18 11:24 ` [PATCH 06/12] riscv: extable: use `ex` for `exception_table_entry` Jisheng Zhang 2021-11-18 11:24 ` Jisheng Zhang 2021-11-18 11:25 ` [PATCH 07/12] riscv: lib: uaccess: fold fixups into body Jisheng Zhang 2021-11-18 11:25 ` Jisheng Zhang 2021-11-18 11:25 ` [PATCH 08/12] riscv: extable: consolidate definitions Jisheng Zhang 2021-11-18 11:25 ` Jisheng Zhang 2021-11-18 11:26 ` [PATCH 09/12] riscv: extable: add `type` and `data` fields Jisheng Zhang 2021-11-18 11:26 ` Jisheng Zhang 2021-11-18 11:42 ` Jisheng Zhang 2021-11-18 11:42 ` Jisheng Zhang 2021-11-18 15:21 ` Mark Rutland 2021-11-18 15:21 ` Mark Rutland 2022-01-06 3:21 ` Palmer Dabbelt 2022-01-06 3:21 ` Palmer Dabbelt 2022-01-06 10:23 ` Mark Rutland 2022-01-06 10:23 ` Mark Rutland 2021-11-19 2:35 ` tongtiangen 2021-11-19 2:35 ` tongtiangen 2021-11-18 11:26 ` Jisheng Zhang [this message] 2021-11-18 11:26 ` [PATCH 10/12] riscv: add gpr-num.h Jisheng Zhang 2021-11-18 11:26 ` [PATCH 11/12] riscv: extable: add a dedicated uaccess handler Jisheng Zhang 2021-11-18 11:26 ` Jisheng Zhang 2021-11-18 17:31 ` kernel test robot 2022-01-20 18:15 ` Mayuresh Chitale 2022-01-20 18:15 ` Mayuresh Chitale 2022-01-21 12:16 ` Jisheng Zhang 2022-01-21 12:16 ` Jisheng Zhang 2022-01-23 9:12 ` Jisheng Zhang 2022-01-23 9:12 ` Jisheng Zhang 2022-01-24 17:02 ` Mayuresh Chitale 2022-01-24 17:02 ` Mayuresh Chitale 2021-11-18 11:27 ` [PATCH 12/12] riscv: vmlinux.lds.S|vmlinux-xip.lds.S: remove `.fixup` section Jisheng Zhang 2021-11-18 11:27 ` Jisheng Zhang
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