From: Maxim Levitsky <mlevitsk@redhat.com> To: linux-kernel@vger.kernel.org Cc: David Woodhouse <dwmw@amazon.co.uk>, Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>, Joerg Roedel <joro@8bytes.org>, Thomas Gleixner <tglx@linutronix.de>, iommu@lists.linux-foundation.org (open list:AMD IOMMU (AMD-VI)), Will Deacon <will@kernel.org>, Maxim Levitsky <mlevitsk@redhat.com> Subject: [PATCH 3/5] iommu/amd: x2apic mode: setup the INTX registers on mask/unmask Date: Tue, 23 Nov 2021 18:10:36 +0200 [thread overview] Message-ID: <20211123161038.48009-4-mlevitsk@redhat.com> (raw) In-Reply-To: <20211123161038.48009-1-mlevitsk@redhat.com> This is more logically correct and will also allow us to to use mask/unmask logic to restore INTX setttings after the resume from s3/s4. Fixes: 66929812955bb ("iommu/amd: Add support for X2APIC IOMMU interrupts") Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com> --- drivers/iommu/amd/init.c | 65 ++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index b905604f434e1..9e895bb8086a6 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2015,48 +2015,18 @@ union intcapxt { }; } __attribute__ ((packed)); -/* - * There isn't really any need to mask/unmask at the irqchip level because - * the 64-bit INTCAPXT registers can be updated atomically without tearing - * when the affinity is being updated. - */ -static void intcapxt_unmask_irq(struct irq_data *data) -{ -} - -static void intcapxt_mask_irq(struct irq_data *data) -{ -} static struct irq_chip intcapxt_controller; static int intcapxt_irqdomain_activate(struct irq_domain *domain, struct irq_data *irqd, bool reserve) { - struct amd_iommu *iommu = irqd->chip_data; - struct irq_cfg *cfg = irqd_cfg(irqd); - union intcapxt xt; - - xt.capxt = 0ULL; - xt.dest_mode_logical = apic->dest_mode_logical; - xt.vector = cfg->vector; - xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); - xt.destid_24_31 = cfg->dest_apicid >> 24; - - /** - * Current IOMMU implemtation uses the same IRQ for all - * 3 IOMMU interrupts. - */ - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); return 0; } static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, struct irq_data *irqd) { - intcapxt_mask_irq(irqd); } @@ -2090,6 +2060,38 @@ static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq irq_domain_free_irqs_top(domain, virq, nr_irqs); } + +static void intcapxt_unmask_irq(struct irq_data *irqd) +{ + struct amd_iommu *iommu = irqd->chip_data; + struct irq_cfg *cfg = irqd_cfg(irqd); + union intcapxt xt; + + xt.capxt = 0ULL; + xt.dest_mode_logical = apic->dest_mode_logical; + xt.vector = cfg->vector; + xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); + xt.destid_24_31 = cfg->dest_apicid >> 24; + + /** + * Current IOMMU implementation uses the same IRQ for all + * 3 IOMMU interrupts. + */ + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); +} + +static void intcapxt_mask_irq(struct irq_data *irqd) +{ + struct amd_iommu *iommu = irqd->chip_data; + + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); +} + + static int intcapxt_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) { @@ -2099,8 +2101,7 @@ static int intcapxt_set_affinity(struct irq_data *irqd, ret = parent->chip->irq_set_affinity(parent, mask, force); if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) return ret; - - return intcapxt_irqdomain_activate(irqd->domain, irqd, false); + return 0; } static struct irq_chip intcapxt_controller = { -- 2.26.3
WARNING: multiple messages have this Message-ID (diff)
From: Maxim Levitsky <mlevitsk@redhat.com> To: linux-kernel@vger.kernel.org Cc: Maxim Levitsky <mlevitsk@redhat.com>, "open list:AMD IOMMU AMD-VI" <iommu@lists.linux-foundation.org>, Thomas Gleixner <tglx@linutronix.de>, Will Deacon <will@kernel.org>, David Woodhouse <dwmw@amazon.co.uk> Subject: [PATCH 3/5] iommu/amd: x2apic mode: setup the INTX registers on mask/unmask Date: Tue, 23 Nov 2021 18:10:36 +0200 [thread overview] Message-ID: <20211123161038.48009-4-mlevitsk@redhat.com> (raw) In-Reply-To: <20211123161038.48009-1-mlevitsk@redhat.com> This is more logically correct and will also allow us to to use mask/unmask logic to restore INTX setttings after the resume from s3/s4. Fixes: 66929812955bb ("iommu/amd: Add support for X2APIC IOMMU interrupts") Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com> --- drivers/iommu/amd/init.c | 65 ++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index b905604f434e1..9e895bb8086a6 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2015,48 +2015,18 @@ union intcapxt { }; } __attribute__ ((packed)); -/* - * There isn't really any need to mask/unmask at the irqchip level because - * the 64-bit INTCAPXT registers can be updated atomically without tearing - * when the affinity is being updated. - */ -static void intcapxt_unmask_irq(struct irq_data *data) -{ -} - -static void intcapxt_mask_irq(struct irq_data *data) -{ -} static struct irq_chip intcapxt_controller; static int intcapxt_irqdomain_activate(struct irq_domain *domain, struct irq_data *irqd, bool reserve) { - struct amd_iommu *iommu = irqd->chip_data; - struct irq_cfg *cfg = irqd_cfg(irqd); - union intcapxt xt; - - xt.capxt = 0ULL; - xt.dest_mode_logical = apic->dest_mode_logical; - xt.vector = cfg->vector; - xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); - xt.destid_24_31 = cfg->dest_apicid >> 24; - - /** - * Current IOMMU implemtation uses the same IRQ for all - * 3 IOMMU interrupts. - */ - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); - writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); return 0; } static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, struct irq_data *irqd) { - intcapxt_mask_irq(irqd); } @@ -2090,6 +2060,38 @@ static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq irq_domain_free_irqs_top(domain, virq, nr_irqs); } + +static void intcapxt_unmask_irq(struct irq_data *irqd) +{ + struct amd_iommu *iommu = irqd->chip_data; + struct irq_cfg *cfg = irqd_cfg(irqd); + union intcapxt xt; + + xt.capxt = 0ULL; + xt.dest_mode_logical = apic->dest_mode_logical; + xt.vector = cfg->vector; + xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); + xt.destid_24_31 = cfg->dest_apicid >> 24; + + /** + * Current IOMMU implementation uses the same IRQ for all + * 3 IOMMU interrupts. + */ + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); + writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); +} + +static void intcapxt_mask_irq(struct irq_data *irqd) +{ + struct amd_iommu *iommu = irqd->chip_data; + + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); + writeq(0, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); +} + + static int intcapxt_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) { @@ -2099,8 +2101,7 @@ static int intcapxt_set_affinity(struct irq_data *irqd, ret = parent->chip->irq_set_affinity(parent, mask, force); if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) return ret; - - return intcapxt_irqdomain_activate(irqd->domain, irqd, false); + return 0; } static struct irq_chip intcapxt_controller = { -- 2.26.3 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2021-11-23 16:11 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-23 16:10 [PATCH 0/5] iommu/amd: fixes for suspend/resume Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky 2021-11-23 16:10 ` [PATCH 1/5] iommu/amd: restore GA log/tail pointer on host resume Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky 2021-11-23 16:10 ` [PATCH 2/5] iommu/amd: x2apic mode: re-enable after resume Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky [this message] 2021-11-23 16:10 ` [PATCH 3/5] iommu/amd: x2apic mode: setup the INTX registers on mask/unmask Maxim Levitsky 2021-11-23 16:10 ` [PATCH 4/5] iommu/amd: x2apic mode: mask/unmask interrupts on suspend/resume Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky 2021-11-23 16:10 ` [PATCH 5/5] iommu/amd: remove useless irq affinity notifier Maxim Levitsky 2021-11-23 16:10 ` Maxim Levitsky 2021-12-01 23:08 ` [PATCH 0/5] iommu/amd: fixes for suspend/resume Maxim Levitsky 2021-12-01 23:08 ` Maxim Levitsky 2021-12-10 8:00 ` Maxim Levitsky 2021-12-10 8:00 ` Maxim Levitsky 2021-12-06 14:01 ` Joerg Roedel 2021-12-06 14:01 ` Joerg Roedel 2021-12-17 8:31 ` Joerg Roedel 2021-12-17 8:31 ` Joerg Roedel 2022-01-25 15:08 ` Mike Lothian 2022-01-25 15:08 ` Mike Lothian 2022-01-25 19:26 ` Maxim Levitsky 2022-01-25 19:26 ` Maxim Levitsky 2022-01-25 23:25 ` Mike Lothian 2022-01-25 23:25 ` Mike Lothian 2022-01-26 7:34 ` Maxim Levitsky 2022-01-26 7:34 ` Maxim Levitsky 2022-01-26 9:54 ` Mike Lothian 2022-01-26 9:54 ` Mike Lothian 2022-01-26 10:12 ` Maxim Levitsky 2022-01-26 10:12 ` Maxim Levitsky 2022-01-27 0:39 ` Mike Lothian 2022-01-27 0:39 ` Mike Lothian 2022-01-27 10:22 ` Maxim Levitsky 2022-01-27 10:22 ` Maxim Levitsky 2022-01-27 10:50 ` Mike Lothian 2022-01-27 10:50 ` Mike Lothian
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