From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
Date: Fri, 3 Dec 2021 11:51:49 +0000 [thread overview]
Message-ID: <20211203115154.31864-2-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20211203115154.31864-1-biju.das.jz@bp.renesas.com>
Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index a91ccad6329b..0962f25cd3f0 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -32,9 +32,9 @@ enum clk_ids {
CLK_PLL3_400,
CLK_PLL3_533,
CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_2,
CLK_PLL3_DIV2_4,
CLK_PLL3_DIV2_4_2,
- CLK_PLL3_DIV4,
CLK_SEL_PLL3_3,
CLK_DIV_PLL3_C,
CLK_PLL4,
@@ -106,9 +106,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
- DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
--
2.17.1
next prev parent reply other threads:[~2021-12-03 11:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 11:51 [PATCH 0/6] Add Mali-G31 GPU support for RZ/G2L SoC Biju Das
2021-12-03 11:51 ` Biju Das
2021-12-03 11:51 ` Biju Das [this message]
2021-12-06 13:08 ` [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 2/6] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das
2021-12-06 13:08 ` Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries Biju Das
2021-12-06 13:10 ` Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Biju Das
2021-12-03 11:51 ` Biju Das
2021-12-06 13:24 ` Geert Uytterhoeven
2021-12-06 13:24 ` Geert Uytterhoeven
2021-12-06 13:47 ` Biju Das
2021-12-06 13:47 ` Biju Das
2021-12-03 11:51 ` [PATCH 5/6] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das
2021-12-06 13:30 ` Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 6/6] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
2021-12-06 13:34 ` Geert Uytterhoeven
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