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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Biju Das <biju.das@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries
Date: Fri,  3 Dec 2021 11:51:51 +0000	[thread overview]
Message-ID: <20211203115154.31864-4-biju.das.jz@bp.renesas.com> (raw)
In-Reply-To: <20211203115154.31864-1-biju.das.jz@bp.renesas.com>

Add GPU clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 85132b6c97b7..79042bf46fe8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -198,6 +198,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 				0x554, 6),
 	DEF_MOD("sdhi1_aclk",	R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
 				0x554, 7),
+	DEF_MOD("gpu_clk",	R9A07G044_GPU_CLK, R9A07G044_CLK_G,
+				0x558, 0),
+	DEF_MOD("gpu_axi_clk",	R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
+				0x558, 1),
+	DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
+				0x558, 2),
 	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
 				0x570, 0),
 	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -285,6 +291,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
 	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
 	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
+	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
+	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
+	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
 	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
 	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
 	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
-- 
2.17.1


  parent reply	other threads:[~2021-12-03 11:52 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-03 11:51 [PATCH 0/6] Add Mali-G31 GPU support for RZ/G2L SoC Biju Das
2021-12-03 11:51 ` Biju Das
2021-12-03 11:51 ` [PATCH 1/6] clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro Biju Das
2021-12-06 13:08   ` Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 2/6] clk: renesas: r9a07g044: Add mux and divider for G clock Biju Das
2021-12-06 13:08   ` Geert Uytterhoeven
2021-12-03 11:51 ` Biju Das [this message]
2021-12-06 13:10   ` [PATCH 3/6] clk: renesas: r9a07g044: Add GPU clock and reset entries Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 4/6] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Biju Das
2021-12-03 11:51   ` Biju Das
2021-12-06 13:24   ` Geert Uytterhoeven
2021-12-06 13:24     ` Geert Uytterhoeven
2021-12-06 13:47     ` Biju Das
2021-12-06 13:47       ` Biju Das
2021-12-03 11:51 ` [PATCH 5/6] arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node Biju Das
2021-12-06 13:30   ` Geert Uytterhoeven
2021-12-03 11:51 ` [PATCH 6/6] arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator Biju Das
2021-12-06 13:34   ` Geert Uytterhoeven

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