From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 0/6] drm/meson: add support for MIPI DSI Display
Date: Fri, 7 Jan 2022 15:55:09 +0100 [thread overview]
Message-ID: <20220107145515.613009-1-narmstrong@baylibre.com> (raw)
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.
This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.
The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- the AXG has a single clock source for both transceiver + pixel, which makes it an
exception instead of a rule, it's simpler to add support for G12A then add AXG on it
- previous glue code was a single monolitic code mixing encoders & bridges, this version
is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
single-clock DSI support specific case on top of this.
[1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@baylibre.com
Neil Armstrong (6):
dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
dt-bindings: display: meson-vpu: add third DPI output port
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
drm/meson: vclk: add DSI clock config
drm/meson: add DSI encoder
drm/meson: add support for MIPI-DSI transceiver
.../display/amlogic,meson-dw-mipi-dsi.yaml | 118 ++++++
.../bindings/display/amlogic,meson-vpu.yaml | 5 +
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 3 +-
drivers/gpu/drm/meson/meson_drv.c | 7 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 383 ++++++++++++++++++
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 115 ++++++
drivers/gpu/drm/meson/meson_encoder_dsi.c | 159 ++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 +
drivers/gpu/drm/meson/meson_vclk.c | 47 +++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
14 files changed, 1092 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 0/6] drm/meson: add support for MIPI DSI Display
Date: Fri, 7 Jan 2022 15:55:09 +0100 [thread overview]
Message-ID: <20220107145515.613009-1-narmstrong@baylibre.com> (raw)
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.
This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.
The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- the AXG has a single clock source for both transceiver + pixel, which makes it an
exception instead of a rule, it's simpler to add support for G12A then add AXG on it
- previous glue code was a single monolitic code mixing encoders & bridges, this version
is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
single-clock DSI support specific case on top of this.
[1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@baylibre.com
Neil Armstrong (6):
dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
dt-bindings: display: meson-vpu: add third DPI output port
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
drm/meson: vclk: add DSI clock config
drm/meson: add DSI encoder
drm/meson: add support for MIPI-DSI transceiver
.../display/amlogic,meson-dw-mipi-dsi.yaml | 118 ++++++
.../bindings/display/amlogic,meson-vpu.yaml | 5 +
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 3 +-
drivers/gpu/drm/meson/meson_drv.c | 7 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 383 ++++++++++++++++++
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 115 ++++++
drivers/gpu/drm/meson/meson_encoder_dsi.c | 159 ++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 +
drivers/gpu/drm/meson/meson_vclk.c | 47 +++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
14 files changed, 1092 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 0/6] drm/meson: add support for MIPI DSI Display
Date: Fri, 7 Jan 2022 15:55:09 +0100 [thread overview]
Message-ID: <20220107145515.613009-1-narmstrong@baylibre.com> (raw)
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.
This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.
The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- the AXG has a single clock source for both transceiver + pixel, which makes it an
exception instead of a rule, it's simpler to add support for G12A then add AXG on it
- previous glue code was a single monolitic code mixing encoders & bridges, this version
is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
single-clock DSI support specific case on top of this.
[1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@baylibre.com
Neil Armstrong (6):
dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
dt-bindings: display: meson-vpu: add third DPI output port
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
drm/meson: vclk: add DSI clock config
drm/meson: add DSI encoder
drm/meson: add support for MIPI-DSI transceiver
.../display/amlogic,meson-dw-mipi-dsi.yaml | 118 ++++++
.../bindings/display/amlogic,meson-vpu.yaml | 5 +
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 3 +-
drivers/gpu/drm/meson/meson_drv.c | 7 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 383 ++++++++++++++++++
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 115 ++++++
drivers/gpu/drm/meson/meson_encoder_dsi.c | 159 ++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 +
drivers/gpu/drm/meson/meson_vclk.c | 47 +++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
14 files changed, 1092 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Neil Armstrong <narmstrong@baylibre.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 0/6] drm/meson: add support for MIPI DSI Display
Date: Fri, 7 Jan 2022 15:55:09 +0100 [thread overview]
Message-ID: <20220107145515.613009-1-narmstrong@baylibre.com> (raw)
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.
This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.
The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- the AXG has a single clock source for both transceiver + pixel, which makes it an
exception instead of a rule, it's simpler to add support for G12A then add AXG on it
- previous glue code was a single monolitic code mixing encoders & bridges, this version
is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
single-clock DSI support specific case on top of this.
[1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@baylibre.com
Neil Armstrong (6):
dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
dt-bindings: display: meson-vpu: add third DPI output port
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
drm/meson: vclk: add DSI clock config
drm/meson: add DSI encoder
drm/meson: add support for MIPI-DSI transceiver
.../display/amlogic,meson-dw-mipi-dsi.yaml | 118 ++++++
.../bindings/display/amlogic,meson-vpu.yaml | 5 +
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 3 +-
drivers/gpu/drm/meson/meson_drv.c | 7 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 383 ++++++++++++++++++
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 115 ++++++
drivers/gpu/drm/meson/meson_encoder_dsi.c | 159 ++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.h | 12 +
drivers/gpu/drm/meson/meson_vclk.c | 47 +++
drivers/gpu/drm/meson/meson_vclk.h | 1 +
drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
14 files changed, 1092 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.h
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.c
create mode 100644 drivers/gpu/drm/meson/meson_encoder_dsi.h
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-01-07 14:55 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 14:55 Neil Armstrong [this message]
2022-01-07 14:55 ` [PATCH 0/6] drm/meson: add support for MIPI DSI Display Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` [PATCH 1/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-07 14:55 ` [PATCH 2/6] dt-bindings: display: meson-vpu: add third DPI output port Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-07 22:14 ` Martin Blumenstingl
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-12 1:54 ` Rob Herring
2022-01-07 14:55 ` [PATCH 3/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-07 22:33 ` Martin Blumenstingl
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-10 9:45 ` Neil Armstrong
2022-01-07 14:55 ` [PATCH 4/6] drm/meson: vclk: add DSI clock config Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` [PATCH 5/6] drm/meson: add DSI encoder Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-07 22:35 ` Martin Blumenstingl
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-10 9:46 ` Neil Armstrong
2022-01-08 18:54 ` kernel test robot
2022-01-08 18:54 ` kernel test robot
2022-01-07 14:55 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 14:55 ` Neil Armstrong
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
2022-01-10 9:51 ` Neil Armstrong
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