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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: danielhb413@gmail.com, richard.henderson@linaro.org,
	groug@kaod.org, clg@kaod.org,
	Matheus Ferst <matheus.ferst@eldorado.org.br>,
	david@gibson.dropbear.id.au
Subject: [PATCH v2 28/38] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
Date: Tue, 25 Jan 2022 09:19:33 -0300	[thread overview]
Message-ID: <20220125121943.3269077-29-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20220125121943.3269077-1-matheus.ferst@eldorado.org.br>

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Implement the following PowerISA v3.0 instuctions:
xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd]
xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round
             to Odd]
xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision [using
              round to Odd]
xsnmsubqp[o]: VSX Scalar Negative Multiply-Subtract Quad-Precision
              [using round to Odd]

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/fpu_helper.c             | 42 +++++++++++++++++++++++++++++
 target/ppc/helper.h                 |  9 +++++++
 target/ppc/insn32.decode            |  4 +++
 target/ppc/translate/vsx-impl.c.inc | 25 +++++++++++++++++
 4 files changed, 80 insertions(+)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 2b7766ddb6..cd4e07ed5b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2222,6 +2222,48 @@ VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
 
+/*
+ * VSX_MADDQ - VSX floating point quad-precision muliply/add
+ *   op    - instruction mnemonic
+ *   maddflgs - flags for the float*muladd routine that control the
+ *           various forms (madd, msub, nmadd, nmsub)
+ *   ro    - round to odd
+ */
+#define VSX_MADDQ(op, maddflgs, ro)                                            \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *s1, ppc_vsr_t *s2,\
+                 ppc_vsr_t *s3)                                                \
+{                                                                              \
+    ppc_vsr_t t = *xt;                                                         \
+                                                                               \
+    helper_reset_fpstatus(env);                                                \
+                                                                               \
+    float_status tstat = env->fp_status;                                       \
+    set_float_exception_flags(0, &tstat);                                      \
+    if (ro) {                                                                  \
+        tstat.float_rounding_mode = float_round_to_odd;                        \
+    }                                                                          \
+    t.f128 = float128_muladd(s1->f128, s3->f128, s2->f128, maddflgs, &tstat);  \
+    env->fp_status.float_exception_flags |= tstat.float_exception_flags;       \
+                                                                               \
+    if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {          \
+        float_invalid_op_madd(env, tstat.float_exception_flags,                \
+                              false, GETPC());                                 \
+    }                                                                          \
+                                                                               \
+    helper_compute_fprf_float128(env, t.f128);                                 \
+    *xt = t;                                                                   \
+    do_float_check_status(env, GETPC());                                       \
+}
+
+VSX_MADDQ(XSMADDQP, MADD_FLGS, 0)
+VSX_MADDQ(XSMADDQPO, MADD_FLGS, 1)
+VSX_MADDQ(XSMSUBQP, MSUB_FLGS, 0)
+VSX_MADDQ(XSMSUBQPO, MSUB_FLGS, 1)
+VSX_MADDQ(XSNMADDQP, NMADD_FLGS, 0)
+VSX_MADDQ(XSNMADDQPO, NMADD_FLGS, 1)
+VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
+VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
+
 /*
  * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
  *   op    - instruction mnemonic
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2a88f2b904..c2c9cff175 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -430,6 +430,15 @@ DEF_HELPER_5(XSMSUBSP, void, env, vsr, vsr, vsr, vsr)
 DEF_HELPER_5(XSNMADDSP, void, env, vsr, vsr, vsr, vsr)
 DEF_HELPER_5(XSNMSUBSP, void, env, vsr, vsr, vsr, vsr)
 
+DEF_HELPER_5(XSMADDQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMADDQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBQPO, void, env, vsr, vsr, vsr, vsr)
+
 DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr)
 DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr)
 DEF_HELPER_4(xvmuldp, void, env, vsr, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 84bc8b1168..c16b990a00 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -549,21 +549,25 @@ XSMADDADP       111100 ..... ..... ..... 00100001 . . . @XX3
 XSMADDMDP       111100 ..... ..... ..... 00101001 . . . @XX3
 XSMADDASP       111100 ..... ..... ..... 00000001 . . . @XX3
 XSMADDMSP       111100 ..... ..... ..... 00001001 . . . @XX3
+XSMADDQP        111111 ..... ..... ..... 0110000100 .   @X_rc
 
 XSMSUBADP       111100 ..... ..... ..... 00110001 . . . @XX3
 XSMSUBMDP       111100 ..... ..... ..... 00111001 . . . @XX3
 XSMSUBASP       111100 ..... ..... ..... 00010001 . . . @XX3
 XSMSUBMSP       111100 ..... ..... ..... 00011001 . . . @XX3
+XSMSUBQP        111111 ..... ..... ..... 0110100100 .   @X_rc
 
 XSNMADDASP      111100 ..... ..... ..... 10000001 . . . @XX3
 XSNMADDMSP      111100 ..... ..... ..... 10001001 . . . @XX3
 XSNMADDADP      111100 ..... ..... ..... 10100001 . . . @XX3
 XSNMADDMDP      111100 ..... ..... ..... 10101001 . . . @XX3
+XSNMADDQP       111111 ..... ..... ..... 0111000100 .   @X_rc
 
 XSNMSUBASP      111100 ..... ..... ..... 10010001 . . . @XX3
 XSNMSUBMSP      111100 ..... ..... ..... 10011001 . . . @XX3
 XSNMSUBADP      111100 ..... ..... ..... 10110001 . . . @XX3
 XSNMSUBMDP      111100 ..... ..... ..... 10111001 . . . @XX3
+XSNMSUBQP       111111 ..... ..... ..... 0111100100 .   @X_rc
 
 ## VSX splat instruction
 
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index be91b8d053..7764b1e5c2 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1331,6 +1331,31 @@ TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
 TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
 TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
 
+static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a,
+        void (gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr),
+        void (gen_helper_ro)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+    int vrt, vra, vrb;
+
+    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+    REQUIRE_VSX(ctx);
+
+    vrt = a->rt + 32;
+    vra = a->ra + 32;
+    vrb = a->rb + 32;
+
+    if (a->rc) {
+        return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper_ro);
+    }
+
+    return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper);
+}
+
+TRANS(XSMADDQP, do_xsmadd_X, gen_helper_XSMADDQP, gen_helper_XSMADDQPO)
+TRANS(XSMSUBQP, do_xsmadd_X, gen_helper_XSMSUBQP, gen_helper_XSMSUBQPO)
+TRANS(XSNMADDQP, do_xsmadd_X, gen_helper_XSNMADDQP, gen_helper_XSNMADDQPO)
+TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO)
+
 #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type)             \
 static void gen_##name(DisasContext *ctx)                                     \
 {                                                                             \
-- 
2.25.1



  parent reply	other threads:[~2022-01-25 14:33 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25 12:19 [PATCH v2 00/38] target/ppc: PowerISA Vector/VSX instruction batch matheus.ferst
2022-01-25 12:19 ` [PATCH v2 01/38] target/ppc: Introduce TRANS*FLAGS macros matheus.ferst
2022-01-25 12:19 ` [PATCH v2 02/38] target/ppc: moved vector even and odd multiplication to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 03/38] target/ppc: Moved vector multiply high and low " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 04/38] target/ppc: vmulh* instructions use gvec matheus.ferst
2022-01-25 12:19 ` [PATCH v2 05/38] target/ppc: Implement vmsumcud instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 06/38] target/ppc: Implement vmsumudm instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 07/38] target/ppc: Move vexts[bhw]2[wd] to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 08/38] target/ppc: Implement vextsd2q matheus.ferst
2022-01-25 12:19 ` [PATCH v2 09/38] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 10/38] target/ppc: Move Vector Compare Not Equal or Zero " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 11/38] target/ppc: Implement Vector Compare Equal Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 12/38] target/ppc: Implement Vector Compare Greater Than Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 13/38] target/ppc: Implement Vector Compare Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 14/38] target/ppc: implement vstri[bh][lr] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 15/38] target/ppc: implement vclrlb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 16/38] target/ppc: implement vclrrb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 17/38] target/ppc: implement vcntmb[bhwd] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 18/38] target/ppc: implement vgnb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 19/38] target/ppc: Move vsel and vperm/vpermr to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 20/38] target/ppc: Move xxsel " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 21/38] target/ppc: move xxperm/xxpermr " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 22/38] target/ppc: Move xxpermdi " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 23/38] target/ppc: Implement xxpermx instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 24/38] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i matheus.ferst
2022-01-25 12:19 ` [PATCH v2 25/38] target/ppc: Implement xxeval matheus.ferst
2022-01-25 12:19 ` [PATCH v2 26/38] target/ppc: Implement xxgenpcv[bhwd]m instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 27/38] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree matheus.ferst
2022-01-25 12:19 ` matheus.ferst [this message]
2022-01-25 12:19 ` [PATCH v2 29/38] target/ppc: Implement xvtlsbb instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 30/38] target/ppc: Remove xscmpnedp instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 31/38] target/ppc: Refactor VSX_SCALAR_CMP_DP matheus.ferst
2022-01-25 12:19 ` [PATCH v2 32/38] target/ppc: Implement xscmp{eq,ge,gt}qp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 33/38] target/ppc: Implement do_helper_XX3 and move xxperm* to use it matheus.ferst
2022-01-25 12:19 ` [PATCH v2 34/38] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 35/38] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 matheus.ferst
2022-01-25 12:19 ` [PATCH v2 36/38] target/ppc: Refactor VSX_MAX_MINC helper matheus.ferst
2022-01-25 12:19 ` [PATCH v2 37/38] target/ppc: Implement xs{max,min}cqp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 38/38] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions matheus.ferst

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