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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: "Lucas Mateus Castro \(alqotel\)" <lucas.castro@eldorado.org.br>,
	danielhb413@gmail.com, richard.henderson@linaro.org,
	groug@kaod.org,
	Lucas Mateus Castro <lucas.araujo@eldorado.org.br>,
	clg@kaod.org, Matheus Ferst <matheus.ferst@eldorado.org.br>,
	david@gibson.dropbear.id.au
Subject: [PATCH v2 03/38] target/ppc: Moved vector multiply high and low to decodetree
Date: Tue, 25 Jan 2022 09:19:08 -0300	[thread overview]
Message-ID: <20220125121943.3269077-4-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20220125121943.3269077-1-matheus.ferst@eldorado.org.br>

From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>

Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to
decodetree

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/helper.h                 |  8 ++++----
 target/ppc/insn32.decode            |  6 ++++++
 target/ppc/int_helper.c             |  8 ++++----
 target/ppc/translate/vmx-impl.c.inc | 21 ++++++++++++++++-----
 target/ppc/translate/vmx-ops.c.inc  |  5 -----
 5 files changed, 30 insertions(+), 18 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6f2c3b32e7..02eda1c137 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -207,10 +207,10 @@ DEF_HELPER_3(VMULOUB, void, avr, avr, avr)
 DEF_HELPER_3(VMULOUH, void, avr, avr, avr)
 DEF_HELPER_3(VMULOUW, void, avr, avr, avr)
 DEF_HELPER_3(VMULOUD, void, avr, avr, avr)
-DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
-DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
-DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
-DEF_HELPER_3(vmulhud, void, avr, avr, avr)
+DEF_HELPER_3(VMULHSW, void, avr, avr, avr)
+DEF_HELPER_3(VMULHUW, void, avr, avr, avr)
+DEF_HELPER_3(VMULHSD, void, avr, avr, avr)
+DEF_HELPER_3(VMULHUD, void, avr, avr, avr)
 DEF_HELPER_3(vslo, void, avr, avr, avr)
 DEF_HELPER_3(vsro, void, avr, avr, avr)
 DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index cab372fa44..4774548b3d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -497,3 +497,9 @@ VMULESD         000100 ..... ..... ..... 01111001000    @VX
 VMULOSD         000100 ..... ..... ..... 00111001000    @VX
 VMULEUD         000100 ..... ..... ..... 01011001000    @VX
 VMULOUD         000100 ..... ..... ..... 00011001000    @VX
+
+VMULHSW         000100 ..... ..... ..... 01110001001    @VX
+VMULHUW         000100 ..... ..... ..... 01010001001    @VX
+VMULHSD         000100 ..... ..... ..... 01111001001    @VX
+VMULHUD         000100 ..... ..... ..... 01011001001    @VX
+VMULLD          000100 ..... ..... ..... 00111001001    @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 56b9e9369b..e134162fdd 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1200,7 +1200,7 @@ void helper_VMULOUD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
     mulu64(&r->VsrD(1), &r->VsrD(0), a->VsrD(1), b->VsrD(1));
 }
 
-void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHSW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
 
@@ -1209,7 +1209,7 @@ void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
     }
 }
 
-void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHUW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
 
@@ -1219,7 +1219,7 @@ void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
     }
 }
 
-void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHSD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
     uint64_t discard;
 
@@ -1227,7 +1227,7 @@ void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
     muls64(&discard, &r->u64[1], a->s64[1], b->s64[1]);
 }
 
-void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHUD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
     uint64_t discard;
 
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 430579addd..62d0642226 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -799,11 +799,6 @@ static void trans_vclzd(DisasContext *ctx)
 }
 
 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
-GEN_VXFORM(vmulhuw, 4, 10);
-GEN_VXFORM(vmulhud, 4, 11);
-GEN_VXFORM(vmulhsw, 4, 14);
-GEN_VXFORM(vmulhsd, 4, 15);
 GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
 GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
 GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
@@ -2103,6 +2098,17 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
     return true;
 }
 
+static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VECTOR(ctx);
+
+    tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
+                     avr_full_offset(a->vrb), 16, 16);
+
+    return true;
+}
+
 TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
 TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
 TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
@@ -2120,6 +2126,11 @@ TRANS_FLAGS2(ISA310, VMULOSD, do_vx_helper, gen_helper_VMULOSD)
 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_helper, gen_helper_VMULEUD)
 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_helper, gen_helper_VMULOUD)
 
+TRANS_FLAGS2(ISA310, VMULHSW, do_vx_helper, gen_helper_VMULHSW)
+TRANS_FLAGS2(ISA310, VMULHSD, do_vx_helper, gen_helper_VMULHSD)
+TRANS_FLAGS2(ISA310, VMULHUW, do_vx_helper, gen_helper_VMULHUW)
+TRANS_FLAGS2(ISA310, VMULHUD, do_vx_helper, gen_helper_VMULHUD)
+
 #undef GEN_VR_LDX
 #undef GEN_VR_STX
 #undef GEN_VR_LVE
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index f310b2fbde..914e68e5b0 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -102,11 +102,6 @@ GEN_VXFORM_300(vextubrx, 6, 28),
 GEN_VXFORM_300(vextuhrx, 6, 29),
 GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM_207(vmuluwm, 4, 2),
-GEN_VXFORM_310(vmulld, 4, 7),
-GEN_VXFORM_310(vmulhuw, 4, 10),
-GEN_VXFORM_310(vmulhud, 4, 11),
-GEN_VXFORM_310(vmulhsw, 4, 14),
-GEN_VXFORM_310(vmulhsd, 4, 15),
 GEN_VXFORM(vslb, 2, 4),
 GEN_VXFORM(vslh, 2, 5),
 GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
-- 
2.25.1



  parent reply	other threads:[~2022-01-26  3:02 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25 12:19 [PATCH v2 00/38] target/ppc: PowerISA Vector/VSX instruction batch matheus.ferst
2022-01-25 12:19 ` [PATCH v2 01/38] target/ppc: Introduce TRANS*FLAGS macros matheus.ferst
2022-01-25 12:19 ` [PATCH v2 02/38] target/ppc: moved vector even and odd multiplication to decodetree matheus.ferst
2022-01-25 12:19 ` matheus.ferst [this message]
2022-01-25 12:19 ` [PATCH v2 04/38] target/ppc: vmulh* instructions use gvec matheus.ferst
2022-01-25 12:19 ` [PATCH v2 05/38] target/ppc: Implement vmsumcud instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 06/38] target/ppc: Implement vmsumudm instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 07/38] target/ppc: Move vexts[bhw]2[wd] to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 08/38] target/ppc: Implement vextsd2q matheus.ferst
2022-01-25 12:19 ` [PATCH v2 09/38] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 10/38] target/ppc: Move Vector Compare Not Equal or Zero " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 11/38] target/ppc: Implement Vector Compare Equal Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 12/38] target/ppc: Implement Vector Compare Greater Than Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 13/38] target/ppc: Implement Vector Compare Quadword matheus.ferst
2022-01-25 12:19 ` [PATCH v2 14/38] target/ppc: implement vstri[bh][lr] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 15/38] target/ppc: implement vclrlb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 16/38] target/ppc: implement vclrrb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 17/38] target/ppc: implement vcntmb[bhwd] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 18/38] target/ppc: implement vgnb matheus.ferst
2022-01-25 12:19 ` [PATCH v2 19/38] target/ppc: Move vsel and vperm/vpermr to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 20/38] target/ppc: Move xxsel " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 21/38] target/ppc: move xxperm/xxpermr " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 22/38] target/ppc: Move xxpermdi " matheus.ferst
2022-01-25 12:19 ` [PATCH v2 23/38] target/ppc: Implement xxpermx instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 24/38] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i matheus.ferst
2022-01-25 12:19 ` [PATCH v2 25/38] target/ppc: Implement xxeval matheus.ferst
2022-01-25 12:19 ` [PATCH v2 26/38] target/ppc: Implement xxgenpcv[bhwd]m instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 27/38] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 28/38] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o] matheus.ferst
2022-01-25 12:19 ` [PATCH v2 29/38] target/ppc: Implement xvtlsbb instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 30/38] target/ppc: Remove xscmpnedp instruction matheus.ferst
2022-01-25 12:19 ` [PATCH v2 31/38] target/ppc: Refactor VSX_SCALAR_CMP_DP matheus.ferst
2022-01-25 12:19 ` [PATCH v2 32/38] target/ppc: Implement xscmp{eq,ge,gt}qp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 33/38] target/ppc: Implement do_helper_XX3 and move xxperm* to use it matheus.ferst
2022-01-25 12:19 ` [PATCH v2 34/38] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree matheus.ferst
2022-01-25 12:19 ` [PATCH v2 35/38] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 matheus.ferst
2022-01-25 12:19 ` [PATCH v2 36/38] target/ppc: Refactor VSX_MAX_MINC helper matheus.ferst
2022-01-25 12:19 ` [PATCH v2 37/38] target/ppc: Implement xs{max,min}cqp matheus.ferst
2022-01-25 12:19 ` [PATCH v2 38/38] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions matheus.ferst

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