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From: Mikko Perttunen <mperttunen@nvidia.com>
To: thierry.reding@gmail.com, jonathanh@nvidia.com, joro@8bytes.org,
	will@kernel.org, robh+dt@kernel.org, robin.murphy@arm.com
Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH v3 4/9] gpu: host1x: Program context stream ID on submission
Date: Fri, 18 Feb 2022 13:39:47 +0200	[thread overview]
Message-ID: <20220218113952.3077606-5-mperttunen@nvidia.com> (raw)
In-Reply-To: <20220218113952.3077606-1-mperttunen@nvidia.com>

Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c        | 52 +++++++++++++++++++++--
 drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
 drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
 include/linux/host1x.h                    |  4 ++
 4 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e88..e23e1395c9f4 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+	u32 fence;
+
+	if (!job->context)
+		return;
+
+	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+	/* First, increment a syncpoint on OP_DONE condition.. */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+	/* Wait for syncpoint to increment */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+			host1x_uclass_wait_syncpt_r(), 1),
+		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+	/*
+	 * Now that we know the engine is idle, return to class and
+	 * change stream ID.
+	 */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		HOST1X_OPCODE_NOP);
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setpayload(job->context->stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
 	if (sp->base)
 		synchronize_syncpt_base(job);
 
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
 	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
-	job->syncpt_end = syncval;
-
 	/* add a setclass for modules that require it */
 	if (job->class)
 		host1x_cdma_push(&ch->cdma,
 				 host1x_opcode_setclass(job->class, 0, 0),
 				 HOST1X_OPCODE_NOP);
 
+	/*
+	 * Ensure engine DMA is idle and set new stream ID. May increment
+	 * syncpt max.
+	 */
+	host1x_channel_program_engine_streamid(job);
+
+	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+	job->syncpt_end = syncval;
+
 	submit_gathers(job, syncval - user_syncpt_incrs);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800..5d515745eee7 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfd..82c0cc9bb0b5 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 9d9f1711472b..185ce6c56365 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -321,6 +321,10 @@ struct host1x_job {
 
 	/* Whether host1x-side firewall should be ran for this job or not */
 	bool enable_firewall;
+
+	/* Options for configuring engine data stream ID */
+	struct host1x_context *context;
+	u32 engine_streamid_offset;
 };
 
 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
-- 
2.35.0


WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen <mperttunen@nvidia.com>
To: thierry.reding@gmail.com, jonathanh@nvidia.com, joro@8bytes.org,
	will@kernel.org, robh+dt@kernel.org, robin.murphy@arm.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	Mikko Perttunen <mperttunen@nvidia.com>,
	iommu@lists.linux-foundation.org, linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/9] gpu: host1x: Program context stream ID on submission
Date: Fri, 18 Feb 2022 13:39:47 +0200	[thread overview]
Message-ID: <20220218113952.3077606-5-mperttunen@nvidia.com> (raw)
In-Reply-To: <20220218113952.3077606-1-mperttunen@nvidia.com>

Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c        | 52 +++++++++++++++++++++--
 drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
 drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
 include/linux/host1x.h                    |  4 ++
 4 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e88..e23e1395c9f4 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+	u32 fence;
+
+	if (!job->context)
+		return;
+
+	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+	/* First, increment a syncpoint on OP_DONE condition.. */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+	/* Wait for syncpoint to increment */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+			host1x_uclass_wait_syncpt_r(), 1),
+		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+	/*
+	 * Now that we know the engine is idle, return to class and
+	 * change stream ID.
+	 */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		HOST1X_OPCODE_NOP);
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setpayload(job->context->stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
 	if (sp->base)
 		synchronize_syncpt_base(job);
 
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
 	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
-	job->syncpt_end = syncval;
-
 	/* add a setclass for modules that require it */
 	if (job->class)
 		host1x_cdma_push(&ch->cdma,
 				 host1x_opcode_setclass(job->class, 0, 0),
 				 HOST1X_OPCODE_NOP);
 
+	/*
+	 * Ensure engine DMA is idle and set new stream ID. May increment
+	 * syncpt max.
+	 */
+	host1x_channel_program_engine_streamid(job);
+
+	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+	job->syncpt_end = syncval;
+
 	submit_gathers(job, syncval - user_syncpt_incrs);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800..5d515745eee7 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfd..82c0cc9bb0b5 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 9d9f1711472b..185ce6c56365 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -321,6 +321,10 @@ struct host1x_job {
 
 	/* Whether host1x-side firewall should be ran for this job or not */
 	bool enable_firewall;
+
+	/* Options for configuring engine data stream ID */
+	struct host1x_context *context;
+	u32 engine_streamid_offset;
 };
 
 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
-- 
2.35.0


WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen via iommu <iommu@lists.linux-foundation.org>
To: thierry.reding@gmail.com, jonathanh@nvidia.com, joro@8bytes.org,
	will@kernel.org, robh+dt@kernel.org, robin.murphy@arm.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	Mikko Perttunen <mperttunen@nvidia.com>,
	iommu@lists.linux-foundation.org, linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/9] gpu: host1x: Program context stream ID on submission
Date: Fri, 18 Feb 2022 13:39:47 +0200	[thread overview]
Message-ID: <20220218113952.3077606-5-mperttunen@nvidia.com> (raw)
In-Reply-To: <20220218113952.3077606-1-mperttunen@nvidia.com>

Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c        | 52 +++++++++++++++++++++--
 drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
 drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
 include/linux/host1x.h                    |  4 ++
 4 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e88..e23e1395c9f4 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+	u32 fence;
+
+	if (!job->context)
+		return;
+
+	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+	/* First, increment a syncpoint on OP_DONE condition.. */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+	/* Wait for syncpoint to increment */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+			host1x_uclass_wait_syncpt_r(), 1),
+		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+	/*
+	 * Now that we know the engine is idle, return to class and
+	 * change stream ID.
+	 */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		HOST1X_OPCODE_NOP);
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setpayload(job->context->stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
 	if (sp->base)
 		synchronize_syncpt_base(job);
 
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
 	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
-	job->syncpt_end = syncval;
-
 	/* add a setclass for modules that require it */
 	if (job->class)
 		host1x_cdma_push(&ch->cdma,
 				 host1x_opcode_setclass(job->class, 0, 0),
 				 HOST1X_OPCODE_NOP);
 
+	/*
+	 * Ensure engine DMA is idle and set new stream ID. May increment
+	 * syncpt max.
+	 */
+	host1x_channel_program_engine_streamid(job);
+
+	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+	job->syncpt_end = syncval;
+
 	submit_gathers(job, syncval - user_syncpt_incrs);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800..5d515745eee7 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfd..82c0cc9bb0b5 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 9d9f1711472b..185ce6c56365 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -321,6 +321,10 @@ struct host1x_job {
 
 	/* Whether host1x-side firewall should be ran for this job or not */
 	bool enable_firewall;
+
+	/* Options for configuring engine data stream ID */
+	struct host1x_context *context;
+	u32 engine_streamid_offset;
 };
 
 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
-- 
2.35.0

_______________________________________________
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iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Mikko Perttunen <mperttunen@nvidia.com>
To: thierry.reding@gmail.com, jonathanh@nvidia.com, joro@8bytes.org,
	will@kernel.org, robh+dt@kernel.org, robin.murphy@arm.com
Cc: linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org,
	iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH v3 4/9] gpu: host1x: Program context stream ID on submission
Date: Fri, 18 Feb 2022 13:39:47 +0200	[thread overview]
Message-ID: <20220218113952.3077606-5-mperttunen@nvidia.com> (raw)
In-Reply-To: <20220218113952.3077606-1-mperttunen@nvidia.com>

Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.

Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/gpu/host1x/hw/channel_hw.c        | 52 +++++++++++++++++++++--
 drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
 drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
 include/linux/host1x.h                    |  4 ++
 4 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e88..e23e1395c9f4 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
 #endif
 }
 
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+	u32 fence;
+
+	if (!job->context)
+		return;
+
+	fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+	/* First, increment a syncpoint on OP_DONE condition.. */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+		HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+			HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+	/* Wait for syncpoint to increment */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+			host1x_uclass_wait_syncpt_r(), 1),
+		host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+	/*
+	 * Now that we know the engine is idle, return to class and
+	 * change stream ID.
+	 */
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setclass(job->class, 0, 0),
+		HOST1X_OPCODE_NOP);
+
+	host1x_cdma_push(&job->channel->cdma,
+		host1x_opcode_setpayload(job->context->stream_id),
+		host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
 static int channel_submit(struct host1x_job *job)
 {
 	struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
 	if (sp->base)
 		synchronize_syncpt_base(job);
 
-	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
 	host1x_hw_syncpt_assign_to_channel(host, sp, ch);
 
-	job->syncpt_end = syncval;
-
 	/* add a setclass for modules that require it */
 	if (job->class)
 		host1x_cdma_push(&ch->cdma,
 				 host1x_opcode_setclass(job->class, 0, 0),
 				 HOST1X_OPCODE_NOP);
 
+	/*
+	 * Ensure engine DMA is idle and set new stream ID. May increment
+	 * syncpt max.
+	 */
+	host1x_channel_program_engine_streamid(job);
+
+	syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+	job->syncpt_end = syncval;
+
 	submit_gathers(job, syncval - user_syncpt_incrs);
 
 	/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800..5d515745eee7 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfd..82c0cc9bb0b5 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
 	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
 }
 
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+	return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+	return (9 << 28) | payload;
+}
+
 static inline u32 host1x_opcode_gather_wide(unsigned count)
 {
 	return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 9d9f1711472b..185ce6c56365 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -321,6 +321,10 @@ struct host1x_job {
 
 	/* Whether host1x-side firewall should be ran for this job or not */
 	bool enable_firewall;
+
+	/* Options for configuring engine data stream ID */
+	struct host1x_context *context;
+	u32 engine_streamid_offset;
 };
 
 struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
-- 
2.35.0


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  parent reply	other threads:[~2022-02-18 11:43 UTC|newest]

Thread overview: 147+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-18 11:39 [PATCH v3 0/9] Host1x context isolation support Mikko Perttunen
2022-02-18 11:39 ` Mikko Perttunen
2022-02-18 11:39 ` Mikko Perttunen via iommu
2022-02-18 11:39 ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 1/9] dt-bindings: host1x: Add memory-contexts property Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-21 15:23   ` Robin Murphy
2022-02-21 15:23     ` Robin Murphy
2022-02-21 15:23     ` Robin Murphy
2022-02-21 15:28     ` Mikko Perttunen
2022-02-21 15:28       ` Mikko Perttunen
2022-02-21 15:28       ` Mikko Perttunen
2022-02-21 16:58       ` Robin Murphy
2022-02-21 16:58         ` Robin Murphy
2022-02-21 16:58         ` Robin Murphy
2022-02-21 17:12         ` Mikko Perttunen
2022-02-21 17:12           ` Mikko Perttunen
2022-02-21 17:12           ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 2/9] gpu: host1x: Add context bus Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-19 17:54   ` Dmitry Osipenko
2022-02-19 17:54     ` Dmitry Osipenko
2022-02-19 17:54     ` Dmitry Osipenko
2022-02-19 17:54     ` Dmitry Osipenko
2022-02-19 18:15     ` Dmitry Osipenko
2022-02-19 18:15       ` Dmitry Osipenko
2022-02-19 18:15       ` Dmitry Osipenko
2022-02-19 18:15       ` Dmitry Osipenko
2022-02-22 16:21   ` Christoph Hellwig
2022-02-22 16:21     ` Christoph Hellwig
2022-02-22 16:21     ` Christoph Hellwig
2022-02-22 21:30     ` Robin Murphy
2022-02-22 21:30       ` Robin Murphy
2022-02-22 21:30       ` Robin Murphy
2022-02-22 21:30       ` Robin Murphy
2022-02-23  6:36       ` Christoph Hellwig
2022-02-23  6:36         ` Christoph Hellwig
2022-02-23  6:36         ` Christoph Hellwig
2022-02-18 11:39 ` [PATCH v3 3/9] gpu: host1x: Add context device management code Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-19 17:48   ` Dmitry Osipenko
2022-02-19 17:48     ` Dmitry Osipenko
2022-02-19 17:48     ` Dmitry Osipenko
2022-02-19 17:48     ` Dmitry Osipenko
2022-02-21 11:35     ` Mikko Perttunen
2022-02-21 11:35       ` Mikko Perttunen
2022-02-21 11:35       ` Mikko Perttunen
2022-02-21 11:35       ` Mikko Perttunen
2022-02-19 17:52   ` Dmitry Osipenko
2022-02-19 17:52     ` Dmitry Osipenko
2022-02-19 17:52     ` Dmitry Osipenko
2022-02-19 17:52     ` Dmitry Osipenko
2022-02-21 11:37     ` Mikko Perttunen
2022-02-21 11:37       ` Mikko Perttunen
2022-02-21 11:37       ` Mikko Perttunen
2022-02-21 11:37       ` Mikko Perttunen
2022-02-22 16:24   ` Christoph Hellwig
2022-02-22 16:24     ` Christoph Hellwig
2022-02-22 16:24     ` Christoph Hellwig
2022-02-23  9:44     ` Mikko Perttunen
2022-02-23  9:44       ` Mikko Perttunen
2022-02-23  9:44       ` Mikko Perttunen
2022-02-23  9:44       ` Mikko Perttunen
2022-02-18 11:39 ` Mikko Perttunen [this message]
2022-02-18 11:39   ` [PATCH v3 4/9] gpu: host1x: Program context stream ID on submission Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 5/9] iommu/arm-smmu: Attach to host1x context device bus Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 6/9] arm64: tegra: Add Host1x context stream IDs on Tegra186+ Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 7/9] drm/tegra: falcon: Set DMACTX field on DMA transactions Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 8/9] drm/tegra: vic: Implement get_streamid_offset Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-19 18:49   ` Dmitry Osipenko
2022-02-19 18:49     ` Dmitry Osipenko
2022-02-19 18:49     ` Dmitry Osipenko
2022-02-19 18:49     ` Dmitry Osipenko
2022-02-19 18:54     ` Dmitry Osipenko
2022-02-19 18:54       ` Dmitry Osipenko
2022-02-19 18:54       ` Dmitry Osipenko
2022-02-19 18:54       ` Dmitry Osipenko
2022-02-21 11:44       ` Mikko Perttunen
2022-02-21 11:44         ` Mikko Perttunen
2022-02-21 11:44         ` Mikko Perttunen
2022-02-21 11:44         ` Mikko Perttunen
2022-02-21 20:10         ` Dmitry Osipenko
2022-02-21 20:10           ` Dmitry Osipenko
2022-02-21 20:10           ` Dmitry Osipenko
2022-02-21 20:10           ` Dmitry Osipenko
2022-02-22  8:27           ` Mikko Perttunen
2022-02-22  8:27             ` Mikko Perttunen
2022-02-22  8:27             ` Mikko Perttunen
2022-02-22  8:27             ` Mikko Perttunen
2022-02-22 10:46             ` Dmitry Osipenko
2022-02-22 10:46               ` Dmitry Osipenko
2022-02-22 10:46               ` Dmitry Osipenko
2022-02-22 10:46               ` Dmitry Osipenko
2022-02-22 10:54               ` Mikko Perttunen
2022-02-22 10:54                 ` Mikko Perttunen
2022-02-22 10:54                 ` Mikko Perttunen
2022-02-22 10:54                 ` Mikko Perttunen
2022-02-22 11:02                 ` Dmitry Osipenko
2022-02-22 11:02                   ` Dmitry Osipenko
2022-02-22 11:02                   ` Dmitry Osipenko
2022-02-22 11:02                   ` Dmitry Osipenko
2022-02-21 17:27   ` Robin Murphy
2022-02-21 17:27     ` Robin Murphy
2022-02-21 17:27     ` Robin Murphy
2022-02-21 17:36     ` Mikko Perttunen
2022-02-21 17:36       ` Mikko Perttunen
2022-02-21 17:36       ` Mikko Perttunen
2022-02-18 11:39 ` [PATCH v3 9/9] drm/tegra: Support context isolation Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen
2022-02-18 11:39   ` Mikko Perttunen via iommu
2022-02-18 11:39   ` Mikko Perttunen
2022-02-19 18:35   ` Dmitry Osipenko
2022-02-19 18:35     ` Dmitry Osipenko
2022-02-19 18:35     ` Dmitry Osipenko
2022-02-19 18:35     ` Dmitry Osipenko
2022-02-21 12:06     ` Mikko Perttunen
2022-02-21 12:06       ` Mikko Perttunen
2022-02-21 12:06       ` Mikko Perttunen
2022-02-21 12:06       ` Mikko Perttunen
2022-02-21 20:02       ` Dmitry Osipenko
2022-02-21 20:02         ` Dmitry Osipenko
2022-02-21 20:02         ` Dmitry Osipenko
2022-02-21 20:02         ` Dmitry Osipenko
2022-02-22  8:37         ` Mikko Perttunen
2022-02-22  8:37           ` Mikko Perttunen
2022-02-22  8:37           ` Mikko Perttunen
2022-02-22  8:37           ` Mikko Perttunen

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