From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
mark.cave-ayland@ilande.co.uk, mst@redhat.com,
imammedo@redhat.com, ani@anisinha.ca
Subject: [PATCH v4 05/43] target/loongarch: Add fixed point shift instruction translation
Date: Tue, 17 May 2022 19:29:45 +0800 [thread overview]
Message-ID: <20220517113023.3051143-6-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <20220517113023.3051143-1-yangxiaojuan@loongson.cn>
From: Song Gao <gaosong@loongson.cn>
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insn_trans/trans_shift.c.inc | 106 ++++++++++++++++++
target/loongarch/insns.decode | 22 ++++
target/loongarch/translate.c | 1 +
3 files changed, 129 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_shift.c.inc
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc
new file mode 100644
index 0000000000..5260af2337
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_shift.c.inc
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_shl_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_shr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_sar_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_shl_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_shr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_sar_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+
+ tcg_gen_trunc_tl_i32(t1, src1);
+ tcg_gen_trunc_tl_i32(t2, t0);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+ tcg_gen_ext_i32_tl(dest, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free(t0);
+}
+
+static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_rotr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
+
+ tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ return true;
+}
+
+TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
+TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
+TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
+TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
+TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
+TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
+TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
+TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
+TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
+TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
+TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
+TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
+TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
+TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
+TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8579c11984..673aee4be5 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -23,6 +23,8 @@
#
@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
@r_i20 .... ... imm:s20 rd:5 &r_i
+@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
+@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
@@ -77,3 +79,23 @@ addu16i_d 0001 00 ................ ..... ..... @rr_i16
andi 0000 001101 ............ ..... ..... @rr_ui12
ori 0000 001110 ............ ..... ..... @rr_ui12
xori 0000 001111 ............ ..... ..... @rr_ui12
+
+#
+# Fixed point shift operation instruction
+#
+sll_w 0000 00000001 01110 ..... ..... ..... @rrr
+srl_w 0000 00000001 01111 ..... ..... ..... @rrr
+sra_w 0000 00000001 10000 ..... ..... ..... @rrr
+sll_d 0000 00000001 10001 ..... ..... ..... @rrr
+srl_d 0000 00000001 10010 ..... ..... ..... @rrr
+sra_d 0000 00000001 10011 ..... ..... ..... @rrr
+rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
+rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
+slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
+slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
+srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
+srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
+srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
+srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
+rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
+rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 4a78d4ec8b..169283ad13 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -146,6 +146,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
+#include "insn_trans/trans_shift.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
2.31.1
next prev parent reply other threads:[~2022-05-17 11:52 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 11:29 [PATCH v4 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 01/43] target/loongarch: Add README Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-05-17 11:29 ` Xiaojuan Yang [this message]
2022-05-17 11:29 ` [PATCH v4 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 08/43] target/loongarch: Add fixed point atomic " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 15/43] target/loongarch: Add branch " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-05-18 17:18 ` Richard Henderson
2022-05-17 11:30 ` [PATCH v4 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 30/43] hw/loongarch: Add support loongson3 virt machine type Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-05-18 18:04 ` Richard Henderson
2022-05-19 3:03 ` yangxiaojuan
2022-05-17 11:30 ` [PATCH v4 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-05-18 19:59 ` Richard Henderson
2022-05-19 13:04 ` yangxiaojuan
2022-05-19 15:24 ` Richard Henderson
2022-05-20 10:07 ` yangxiaojuan
2022-05-17 11:30 ` [PATCH v4 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-05-18 20:01 ` Richard Henderson
2022-05-17 11:30 ` [PATCH v4 40/43] hw/loongarch: Add LoongArch ls7a acpi device support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang
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