From: "Víctor Colombo" <victor.colombo@eldorado.org.br>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au,
groug@kaod.org, richard.henderson@linaro.org,
victor.colombo@eldorado.org.br
Subject: [PATCH v2 05/11] target/ppc: Move mffs[.] to decodetree
Date: Mon, 23 May 2022 14:58:01 -0300 [thread overview]
Message-ID: <20220523175807.59333-6-victor.colombo@eldorado.org.br> (raw)
In-Reply-To: <20220523175807.59333-1-victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/insn32.decode | 4 ++++
target/ppc/translate/fp-impl.c.inc | 35 +++++++++++++++---------------
target/ppc/translate/fp-ops.c.inc | 1 -
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 68ea34d608..76bd9e4f57 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -97,6 +97,9 @@
&X_tb rt rb
@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb
+&X_t_rc rt rc:bool
+@X_t_rc ...... rt:5 ..... ..... .......... rc:1 &X_t_rc
+
&X_tb_rc rt rb rc:bool
@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
@@ -323,6 +326,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
### Move To/From FPSCR
+MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index e602cbf0a5..24adf0ad15 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -589,24 +589,6 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_temp_free_i64(tnew_fpscr);
}
-/* mffs */
-static void gen_mffs(DisasContext *ctx)
-{
- TCGv_i64 t0;
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
- t0 = tcg_temp_new_i64();
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- set_fpr(rD(ctx->opcode), t0);
- if (unlikely(Rc(ctx->opcode))) {
- gen_set_cr1_from_fpscr(ctx);
- }
- tcg_temp_free_i64(t0);
-}
-
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
{
TCGv_i64 fpscr = tcg_temp_new_i64();
@@ -634,6 +616,23 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask,
tcg_temp_free_i64(fpscr_masked);
}
+static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
+{
+ TCGv_i64 fpscr;
+
+ REQUIRE_FPU(ctx);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt, UINT64_MAX);
+ if (a->rc) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a)
{
TCGv_i64 fpscr;
diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc
index f7ca1cc8b8..81640553e1 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -75,7 +75,6 @@ GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
-GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
--
2.25.1
next prev parent reply other threads:[~2022-05-23 18:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-23 17:57 [PATCH v2 00/11] BCDA and mffscdrn implementations Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 01/11] target/ppc: Fix insn32.decode style issues Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 02/11] target/ppc: Move mffscrn[i] to decodetree Víctor Colombo
2022-05-23 17:57 ` [PATCH v2 03/11] target/ppc: Move mffsce " Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 04/11] target/ppc: Move mffsl " Víctor Colombo
2022-05-23 17:58 ` Víctor Colombo [this message]
2022-05-23 17:58 ` [PATCH v2 06/11] target/ppc: Implement mffscdrn[i] instructions Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 07/11] tests/tcg/ppc64: Add mffsce test Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 08/11] target/ppc: Add flag for ISA v2.06 BCDA instructions Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 09/11] target/ppc: implement addg6s Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 10/11] target/ppc: implement cbcdtd Víctor Colombo
2022-05-23 17:58 ` [PATCH v2 11/11] target/ppc: implement cdtbcd Víctor Colombo
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