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From: "Paweł Anikiel" <pan@semihalf.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	dinguyen@kernel.org
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, amstan@chromium.org,
	upstream@semihalf.com, "Paweł Anikiel" <pan@semihalf.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
Date: Fri,  3 Jun 2022 11:23:51 +0200	[thread overview]
Message-ID: <20220603092354.141927-3-pan@semihalf.com> (raw)
In-Reply-To: <20220603092354.141927-1-pan@semihalf.com>

The ecc manager is a part of the Arria 10 SoC, move it to the correct
dts.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi             | 10 ++++++++++
 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 12 ------------
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 26bda2557fe8..4370e3cbbb4b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -736,6 +736,16 @@ emac0-tx-ecc@ff8c0c00 {
 					     <37 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			sdmmca-ecc@ff8c2c00 {
+				compatible = "altr,socfpga-sdmmc-ecc";
+				reg = <0xff8c2c00 0x400>;
+				altr,ecc-parent = <&mmc>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					     <47 IRQ_TYPE_LEVEL_HIGH>,
+					     <16 IRQ_TYPE_LEVEL_HIGH>,
+					     <48 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
 			dma-ecc@ff8c8000 {
 				compatible = "altr,socfpga-dma-ecc";
 				reg = <0xff8c8000 0x400>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index 4b21351f2694..b0d20101cd00 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -23,18 +23,6 @@ chosen {
 	};
 };
 
-&eccmgr {
-	sdmmca-ecc@ff8c2c00 {
-		compatible = "altr,socfpga-sdmmc-ecc";
-		reg = <0xff8c2c00 0x400>;
-		altr,ecc-parent = <&mmc>;
-		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
-			     <47 IRQ_TYPE_LEVEL_HIGH>,
-			     <16 IRQ_TYPE_LEVEL_HIGH>,
-			     <48 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-
 &gmac0 {
 	phy-mode = "rgmii";
 	phy-addr = <0xffffffff>; /* probe for phy addr */
-- 
2.36.1.255.ge46751e96f-goog


WARNING: multiple messages have this Message-ID (diff)
From: "Paweł Anikiel" <pan@semihalf.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	dinguyen@kernel.org
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, amstan@chromium.org,
	upstream@semihalf.com, "Paweł Anikiel" <pan@semihalf.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
Date: Fri,  3 Jun 2022 11:23:51 +0200	[thread overview]
Message-ID: <20220603092354.141927-3-pan@semihalf.com> (raw)
In-Reply-To: <20220603092354.141927-1-pan@semihalf.com>

The ecc manager is a part of the Arria 10 SoC, move it to the correct
dts.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi             | 10 ++++++++++
 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 12 ------------
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 26bda2557fe8..4370e3cbbb4b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -736,6 +736,16 @@ emac0-tx-ecc@ff8c0c00 {
 					     <37 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			sdmmca-ecc@ff8c2c00 {
+				compatible = "altr,socfpga-sdmmc-ecc";
+				reg = <0xff8c2c00 0x400>;
+				altr,ecc-parent = <&mmc>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+					     <47 IRQ_TYPE_LEVEL_HIGH>,
+					     <16 IRQ_TYPE_LEVEL_HIGH>,
+					     <48 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
 			dma-ecc@ff8c8000 {
 				compatible = "altr,socfpga-dma-ecc";
 				reg = <0xff8c8000 0x400>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index 4b21351f2694..b0d20101cd00 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -23,18 +23,6 @@ chosen {
 	};
 };
 
-&eccmgr {
-	sdmmca-ecc@ff8c2c00 {
-		compatible = "altr,socfpga-sdmmc-ecc";
-		reg = <0xff8c2c00 0x400>;
-		altr,ecc-parent = <&mmc>;
-		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
-			     <47 IRQ_TYPE_LEVEL_HIGH>,
-			     <16 IRQ_TYPE_LEVEL_HIGH>,
-			     <48 IRQ_TYPE_LEVEL_HIGH>;
-	};
-};
-
 &gmac0 {
 	phy-mode = "rgmii";
 	phy-addr = <0xffffffff>; /* probe for phy addr */
-- 
2.36.1.255.ge46751e96f-goog


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linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-06-03  9:24 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03  9:23 [PATCH v4 0/5] Add Chameleon v3 devicetree Paweł Anikiel
2022-06-03  9:23 ` Paweł Anikiel
2022-06-03  9:23 ` [PATCH v4 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Paweł Anikiel
2022-06-03  9:23   ` Paweł Anikiel
2022-06-03  9:23 ` Paweł Anikiel [this message]
2022-06-03  9:23   ` [PATCH v4 2/5] ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts Paweł Anikiel
2022-06-03  9:23 ` [PATCH v4 3/5] ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts Paweł Anikiel
2022-06-03  9:23   ` Paweł Anikiel
2022-06-03  9:23 ` [PATCH v4 4/5] ARM: dts: socfpga: Add Google Chameleon v3 devicetree Paweł Anikiel
2022-06-03  9:23   ` Paweł Anikiel
2022-06-03  9:23 ` [PATCH v4 5/5] dt-bindings: altera: Add Chameleon v3 board Paweł Anikiel
2022-06-03  9:23   ` Paweł Anikiel
2022-06-03 10:18   ` Krzysztof Kozlowski
2022-06-03 10:18     ` Krzysztof Kozlowski
2022-06-14 15:47 ` [PATCH v4 0/5] Add Chameleon v3 devicetree Dinh Nguyen
2022-06-14 15:47   ` Dinh Nguyen

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