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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v4 06/17] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
Date: Wed,  7 Sep 2022 12:10:46 +0300	[thread overview]
Message-ID: <20220907091057.11572-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220907091057.11572-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.

This should also prevent .get_dplls() from seeing a funky port_clock
for DP even in cases where the readout produces a non-standard
clock and we (for some reason) have decided to not fully recompute
the state to remedy the situation.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 17 +----------------
 drivers/gpu/drm/i915/display/intel_dpll.c    |  6 ++----
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80e077050b67..4e8d30ff998b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6065,20 +6065,6 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-static void intel_modeset_clear_plls(struct intel_atomic_state *state)
-{
-	struct intel_crtc_state *new_crtc_state;
-	struct intel_crtc *crtc;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-		if (!intel_crtc_needs_modeset(new_crtc_state))
-			continue;
-
-		intel_release_shared_dplls(state, crtc);
-	}
-}
-
 /*
  * This implements the workaround described in the "notes" section of the mode
  * set sequence documentation. When going from no pipes or single pipe to
@@ -6912,6 +6898,7 @@ static int intel_atomic_check(struct drm_device *dev,
 			if (ret)
 				goto fail;
 
+			intel_release_shared_dplls(state, crtc);
 			continue;
 		}
 
@@ -6959,8 +6946,6 @@ static int intel_atomic_check(struct drm_device *dev,
 		ret = intel_modeset_calc_cdclk(state);
 		if (ret)
 			return ret;
-
-		intel_modeset_clear_plls(state);
 	}
 
 	ret = intel_atomic_check_crtcs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6b8d90d72e00..4b20541ba760 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+	drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
 
-	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-		return 0;
-
-	if (!crtc_state->hw.enable)
+	if (!crtc_state->hw.enable || crtc_state->shared_dpll)
 		return 0;
 
 	if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
-- 
2.35.1


  parent reply	other threads:[~2022-09-07  9:11 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-07  9:10 [Intel-gfx] [PATCH v4 00/17] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 01/17] drm/i915: Relocate intel_crtc_dotclock() Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 02/17] drm/i915: Shuffle some PLL code around Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 03/17] drm/i915: Extract HAS_DOUBLE_BUFFERED_M_N() Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 04/17] drm/i915/dsi: Extract {vlv, bxt}_get_pclk() Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 05/17] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-09-07  9:10 ` Ville Syrjala [this message]
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 07/17] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 08/17] drm/i915: Compute clocks earlier Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 09/17] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 10/17] drm/i915: Make all clock " Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 11/17] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 12/17] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 13/17] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 14/17] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 15/17] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 16/17] drm/i915: Use a fixed N value always Ville Syrjala
2022-09-07  9:10 ` [Intel-gfx] [PATCH v4 17/17] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-09-07 11:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev7) Patchwork
2022-09-07 11:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-07 12:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-07 17:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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