From: Hal Feng <hal.feng@linux.starfivetech.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Hal Feng <hal.feng@linux.starfivetech.com>, linux-kernel@vger.kernel.org Subject: [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree Date: Thu, 29 Sep 2022 22:32:04 +0800 [thread overview] Message-ID: <20220929143225.17907-10-hal.feng@linux.starfivetech.com> (raw) In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> Store the necessary properties in device tree instead of .c file, in order to apply this reset driver to other StarFive SoCs. Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> --- .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 ++ drivers/reset/reset-starfive-jh7100.c | 50 +++++++++++++------ 3 files changed, 57 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml index 300359a5e14b..3eff3f72a1ed 100644 --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml @@ -20,19 +20,39 @@ properties: "#reset-cells": const: 1 + starfive,assert-offset: + description: Offset of the first ASSERT register + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,status-offset: + description: Offset of the first STATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,nr-resets: + description: Number of reset signals + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg - "#reset-cells" + - starfive,assert-offset + - starfive,status-offset + - starfive,nr-resets additionalProperties: false examples: - | + #include <dt-bindings/reset/starfive-jh7100.h> + reset-controller@11840000 { compatible = "starfive,jh7100-reset"; reg = <0x11840000 0x10000>; #reset-cells = <1>; + starfive,assert-offset = <0x0>; + starfive,status-offset= <0x10>; + starfive,nr-resets = <JH7100_RSTN_END>; }; ... diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..904a93411add 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -145,6 +145,9 @@ compatible = "starfive,jh7100-reset"; reg = <0x0 0x11840000 0x0 0x10000>; #reset-cells = <1>; + starfive,assert-offset = <0x0>; + starfive,status-offset= <0x10>; + starfive,nr-resets = <JH7100_RSTN_END>; }; i2c0: i2c@118b0000 { diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c index 8cba62348a16..d3656e99ae0e 100644 --- a/drivers/reset/reset-starfive-jh7100.c +++ b/drivers/reset/reset-starfive-jh7100.c @@ -14,16 +14,6 @@ #include <dt-bindings/reset/starfive-jh7100.h> -/* register offsets */ -#define JH7100_RESET_ASSERT0 0x00 -#define JH7100_RESET_ASSERT1 0x04 -#define JH7100_RESET_ASSERT2 0x08 -#define JH7100_RESET_ASSERT3 0x0c -#define JH7100_RESET_STATUS0 0x10 -#define JH7100_RESET_STATUS1 0x14 -#define JH7100_RESET_STATUS2 0x18 -#define JH7100_RESET_STATUS3 0x1c - /* * Writing a 1 to the n'th bit of the m'th ASSERT register asserts * line 32m + n, and writing a 0 deasserts the same line. @@ -49,6 +39,10 @@ static const u32 jh7100_reset_asserted[4] = { struct jh7100_reset { struct reset_controller_dev rcdev; struct regmap *regmap; + u32 assert_offset; + u32 status_offset; + u32 nr_resets; + const u32 *asserted; }; static inline struct jh7100_reset * @@ -63,9 +57,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev, struct jh7100_reset *data = jh7100_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); - u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32); - u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32); - u32 done = jh7100_reset_asserted[offset] & mask; + u32 reg_assert = data->assert_offset + offset * sizeof(u32); + u32 reg_status = data->status_offset + offset * sizeof(u32); + u32 done = data->asserted ? data->asserted[offset] & mask : 0; u32 value; int ret; @@ -122,7 +116,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, struct jh7100_reset *data = jh7100_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); - u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32); + u32 reg_status = data->status_offset + offset * sizeof(u32); u32 value; int ret; @@ -130,7 +124,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, if (ret) return ret; - return !((value ^ jh7100_reset_asserted[offset]) & mask); + return !((value ^ data->asserted[offset]) & mask); } static const struct reset_control_ops jh7100_reset_ops = { @@ -143,6 +137,7 @@ static const struct reset_control_ops jh7100_reset_ops = { static int __init jh7100_reset_probe(struct platform_device *pdev) { struct jh7100_reset *data; + int ret; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -155,12 +150,35 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) return PTR_ERR(data->regmap); } + ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset", + &data->assert_offset); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,assert-offset: %d\n", ret); + return ret; + } + + ret = of_property_read_u32(pdev->dev.of_node, "starfive,status-offset", + &data->status_offset); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,status-offset: %d\n", ret); + return ret; + } + + ret = of_property_read_u32(pdev->dev.of_node, "starfive,nr-resets", + &data->nr_resets); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,nr-resets: %d\n", ret); + return ret; + } + data->rcdev.ops = &jh7100_reset_ops; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = JH7100_RSTN_END; + data->rcdev.nr_resets = data->nr_resets; data->rcdev.dev = &pdev->dev; data->rcdev.of_node = pdev->dev.of_node; + data->asserted = jh7100_reset_asserted; + return devm_reset_controller_register(&pdev->dev, &data->rcdev); } -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@linux.starfivetech.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Linus Walleij <linus.walleij@linaro.org>, Emil Renner Berthing <kernel@esmil.dk>, Hal Feng <hal.feng@linux.starfivetech.com>, linux-kernel@vger.kernel.org Subject: [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree Date: Thu, 29 Sep 2022 22:32:04 +0800 [thread overview] Message-ID: <20220929143225.17907-10-hal.feng@linux.starfivetech.com> (raw) In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> Store the necessary properties in device tree instead of .c file, in order to apply this reset driver to other StarFive SoCs. Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> --- .../bindings/reset/starfive,jh7100-reset.yaml | 20 ++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 3 ++ drivers/reset/reset-starfive-jh7100.c | 50 +++++++++++++------ 3 files changed, 57 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml index 300359a5e14b..3eff3f72a1ed 100644 --- a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml +++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml @@ -20,19 +20,39 @@ properties: "#reset-cells": const: 1 + starfive,assert-offset: + description: Offset of the first ASSERT register + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,status-offset: + description: Offset of the first STATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + starfive,nr-resets: + description: Number of reset signals + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg - "#reset-cells" + - starfive,assert-offset + - starfive,status-offset + - starfive,nr-resets additionalProperties: false examples: - | + #include <dt-bindings/reset/starfive-jh7100.h> + reset-controller@11840000 { compatible = "starfive,jh7100-reset"; reg = <0x11840000 0x10000>; #reset-cells = <1>; + starfive,assert-offset = <0x0>; + starfive,status-offset= <0x10>; + starfive,nr-resets = <JH7100_RSTN_END>; }; ... diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..904a93411add 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -145,6 +145,9 @@ compatible = "starfive,jh7100-reset"; reg = <0x0 0x11840000 0x0 0x10000>; #reset-cells = <1>; + starfive,assert-offset = <0x0>; + starfive,status-offset= <0x10>; + starfive,nr-resets = <JH7100_RSTN_END>; }; i2c0: i2c@118b0000 { diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c index 8cba62348a16..d3656e99ae0e 100644 --- a/drivers/reset/reset-starfive-jh7100.c +++ b/drivers/reset/reset-starfive-jh7100.c @@ -14,16 +14,6 @@ #include <dt-bindings/reset/starfive-jh7100.h> -/* register offsets */ -#define JH7100_RESET_ASSERT0 0x00 -#define JH7100_RESET_ASSERT1 0x04 -#define JH7100_RESET_ASSERT2 0x08 -#define JH7100_RESET_ASSERT3 0x0c -#define JH7100_RESET_STATUS0 0x10 -#define JH7100_RESET_STATUS1 0x14 -#define JH7100_RESET_STATUS2 0x18 -#define JH7100_RESET_STATUS3 0x1c - /* * Writing a 1 to the n'th bit of the m'th ASSERT register asserts * line 32m + n, and writing a 0 deasserts the same line. @@ -49,6 +39,10 @@ static const u32 jh7100_reset_asserted[4] = { struct jh7100_reset { struct reset_controller_dev rcdev; struct regmap *regmap; + u32 assert_offset; + u32 status_offset; + u32 nr_resets; + const u32 *asserted; }; static inline struct jh7100_reset * @@ -63,9 +57,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev, struct jh7100_reset *data = jh7100_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); - u32 reg_assert = JH7100_RESET_ASSERT0 + offset * sizeof(u32); - u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32); - u32 done = jh7100_reset_asserted[offset] & mask; + u32 reg_assert = data->assert_offset + offset * sizeof(u32); + u32 reg_status = data->status_offset + offset * sizeof(u32); + u32 done = data->asserted ? data->asserted[offset] & mask : 0; u32 value; int ret; @@ -122,7 +116,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, struct jh7100_reset *data = jh7100_reset_from(rcdev); u32 offset = id / 32; u32 mask = BIT(id % 32); - u32 reg_status = JH7100_RESET_STATUS0 + offset * sizeof(u32); + u32 reg_status = data->status_offset + offset * sizeof(u32); u32 value; int ret; @@ -130,7 +124,7 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, if (ret) return ret; - return !((value ^ jh7100_reset_asserted[offset]) & mask); + return !((value ^ data->asserted[offset]) & mask); } static const struct reset_control_ops jh7100_reset_ops = { @@ -143,6 +137,7 @@ static const struct reset_control_ops jh7100_reset_ops = { static int __init jh7100_reset_probe(struct platform_device *pdev) { struct jh7100_reset *data; + int ret; data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -155,12 +150,35 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) return PTR_ERR(data->regmap); } + ret = of_property_read_u32(pdev->dev.of_node, "starfive,assert-offset", + &data->assert_offset); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,assert-offset: %d\n", ret); + return ret; + } + + ret = of_property_read_u32(pdev->dev.of_node, "starfive,status-offset", + &data->status_offset); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,status-offset: %d\n", ret); + return ret; + } + + ret = of_property_read_u32(pdev->dev.of_node, "starfive,nr-resets", + &data->nr_resets); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get starfive,nr-resets: %d\n", ret); + return ret; + } + data->rcdev.ops = &jh7100_reset_ops; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = JH7100_RSTN_END; + data->rcdev.nr_resets = data->nr_resets; data->rcdev.dev = &pdev->dev; data->rcdev.of_node = pdev->dev.of_node; + data->asserted = jh7100_reset_asserted; + return devm_reset_controller_register(&pdev->dev, &data->rcdev); } -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-09-29 16:08 UTC|newest] Thread overview: 210+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-29 14:31 [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:31 ` [PATCH v1 01/30] dt-bindings: riscv: Add StarFive JH7110 bindings Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-10-08 3:44 ` Hal Feng 2022-10-08 3:44 ` Hal Feng 2022-09-29 14:31 ` [PATCH v1 02/30] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:34 ` Krzysztof Kozlowski 2022-09-29 14:31 ` [PATCH v1 03/30] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:35 ` Krzysztof Kozlowski 2022-09-29 14:35 ` Krzysztof Kozlowski 2022-09-29 14:31 ` [PATCH v1 04/30] dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs Hal Feng 2022-09-29 14:31 ` Hal Feng 2022-09-29 14:36 ` Krzysztof Kozlowski 2022-09-29 14:36 ` Krzysztof Kozlowski 2022-09-29 15:33 ` Conor Dooley 2022-09-29 15:33 ` Conor Dooley 2022-10-03 9:26 ` Ben Dooks 2022-10-03 9:26 ` Ben Dooks 2022-10-08 18:54 ` Hal Feng 2022-10-08 18:54 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 05/30] soc: sifive: l2 cache: Convert to platform driver Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 15:32 ` Conor Dooley 2022-09-29 15:32 ` Conor Dooley 2022-09-29 17:57 ` Ben Dooks 2022-09-29 17:57 ` Ben Dooks 2022-10-05 13:44 ` Emil Renner Berthing 2022-10-05 13:44 ` Emil Renner Berthing 2022-10-05 13:48 ` Ben Dooks 2022-10-05 13:48 ` Ben Dooks 2022-10-05 13:55 ` Emil Renner Berthing 2022-10-05 13:55 ` Emil Renner Berthing 2022-10-05 14:05 ` Conor Dooley 2022-10-05 14:05 ` Conor Dooley 2022-10-08 18:07 ` Hal Feng 2022-10-08 18:07 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 06/30] soc: sifive: l2 cache: Add StarFive JH71x0 support Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 07/30] reset: starfive: jh7100: Use 32bit I/O on 32bit registers Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:32 ` [PATCH v1 08/30] reset: starfive: jh7100: Use regmap APIs to operate registers Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:32 ` Hal Feng [this message] 2022-09-29 14:32 ` [PATCH v1 09/30] reset: starfive: jh7100: Move necessary properties to device tree Hal Feng 2022-09-30 20:49 ` Rob Herring 2022-09-30 20:49 ` Rob Herring 2022-10-05 13:20 ` Emil Renner Berthing 2022-10-05 13:20 ` Emil Renner Berthing 2022-09-29 14:32 ` [PATCH v1 10/30] reset: starfive: Rename 'reset-starfive-jh7100.c' to 'reset-starfive.c' Hal Feng 2022-09-29 14:32 ` Hal Feng 2022-09-29 14:45 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Krzysztof Kozlowski 2022-09-29 14:45 ` Krzysztof Kozlowski 2022-09-29 17:59 ` Conor Dooley 2022-09-29 17:59 ` Conor Dooley 2022-10-01 1:13 ` hal.feng 2022-10-01 1:13 ` hal.feng 2022-09-29 16:35 ` [PATCH v1 11/30] dt-bindings: reset: Add StarFive JH7110 reset definitions Hal Feng 2022-09-29 16:35 ` Hal Feng 2022-09-29 17:51 ` [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset bindings Hal Feng 2022-09-29 17:51 ` Hal Feng 2022-09-29 18:21 ` Rob Herring 2022-09-29 18:21 ` Rob Herring 2022-09-29 18:40 ` Rob Herring 2022-09-29 18:40 ` Rob Herring 2022-09-29 18:43 ` Rob Herring 2022-09-29 18:43 ` Rob Herring 2022-10-11 15:30 ` Hal Feng 2022-10-11 15:30 ` Hal Feng 2022-10-11 16:36 ` Krzysztof Kozlowski 2022-10-11 16:36 ` Krzysztof Kozlowski 2022-10-12 13:16 ` Hal Feng 2022-10-12 13:16 ` Hal Feng 2022-10-12 13:33 ` Krzysztof Kozlowski 2022-10-12 13:33 ` Krzysztof Kozlowski 2022-10-12 14:05 ` Conor Dooley 2022-10-12 14:05 ` Conor Dooley 2022-10-12 15:21 ` Hal Feng 2022-10-12 15:21 ` Hal Feng 2022-10-12 14:53 ` Hal Feng 2022-10-12 14:53 ` Hal Feng 2022-10-12 8:01 ` Emil Renner Berthing 2022-10-12 8:01 ` Emil Renner Berthing 2022-09-29 17:53 ` [PATCH v1 13/30] reset: starfive: Add StarFive JH7110 SoC support Hal Feng 2022-09-29 17:53 ` Hal Feng 2022-09-29 17:54 ` [PATCH v1 14/30] clk: starfive: Factor out common clock driver code Hal Feng 2022-09-29 17:54 ` Hal Feng 2022-09-30 21:43 ` Stephen Boyd 2022-09-30 21:43 ` Stephen Boyd 2022-09-29 17:56 ` [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers Hal Feng 2022-09-29 17:56 ` Hal Feng 2022-09-30 21:48 ` Stephen Boyd 2022-09-30 21:48 ` Stephen Boyd 2022-10-05 13:14 ` Emil Renner Berthing 2022-10-05 13:14 ` Emil Renner Berthing 2022-10-12 23:05 ` Stephen Boyd 2022-10-12 23:05 ` Stephen Boyd 2022-10-23 4:11 ` Hal Feng 2022-10-23 4:11 ` Hal Feng 2022-10-23 10:25 ` Conor Dooley 2022-10-23 10:25 ` Conor Dooley 2022-10-28 3:16 ` Hal Feng 2022-10-28 3:16 ` Hal Feng 2022-10-27 1:26 ` Stephen Boyd 2022-10-27 1:26 ` Stephen Boyd 2022-10-28 2:46 ` Hal Feng 2022-10-28 2:46 ` Hal Feng 2022-09-29 17:56 ` [PATCH v1 16/30] dt-bindings: clock: Add StarFive JH7110 system clock definitions Hal Feng 2022-09-29 17:56 ` Hal Feng 2022-09-29 22:26 ` [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings Hal Feng 2022-09-29 22:26 ` Hal Feng 2022-09-30 1:55 ` Rob Herring 2022-09-30 1:55 ` Rob Herring 2022-09-30 10:58 ` Krzysztof Kozlowski 2022-09-30 10:58 ` Krzysztof Kozlowski 2022-10-11 17:52 ` Hal Feng 2022-10-11 17:52 ` Hal Feng 2022-09-30 1:50 ` [PATCH v1 18/30] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng 2022-09-30 1:50 ` Hal Feng 2022-09-30 5:49 ` [PATCH v1 19/30] dt-bindings: clock: Add StarFive JH7110 always-on definitions Hal Feng 2022-09-30 5:49 ` Hal Feng 2022-09-30 5:56 ` [PATCH v1 20/30] dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings Hal Feng 2022-09-30 5:56 ` Hal Feng 2022-09-30 10:59 ` Krzysztof Kozlowski 2022-09-30 10:59 ` Krzysztof Kozlowski 2022-10-11 18:01 ` Hal Feng 2022-10-11 18:01 ` Hal Feng 2022-09-30 12:51 ` Rob Herring 2022-09-30 12:51 ` Rob Herring 2022-09-30 6:03 ` [PATCH v1 21/30] clk: starfive: Add StarFive JH7110 always-on clock driver Hal Feng 2022-09-30 6:03 ` Hal Feng 2022-09-30 6:08 ` [PATCH v1 22/30] pinctrl: Create subdirectory for StarFive drivers Hal Feng 2022-09-30 6:08 ` Hal Feng 2022-10-04 8:43 ` Linus Walleij 2022-10-04 8:43 ` Linus Walleij 2022-09-30 6:14 ` [PATCH v1 23/30] pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100" Hal Feng 2022-09-30 6:14 ` Hal Feng 2022-09-30 21:28 ` Rob Herring 2022-09-30 21:28 ` Rob Herring 2022-10-04 8:48 ` Linus Walleij 2022-10-04 8:48 ` Linus Walleij 2022-10-04 8:58 ` Conor Dooley 2022-10-04 8:58 ` Conor Dooley 2022-10-04 9:13 ` Linus Walleij 2022-10-04 9:13 ` Linus Walleij 2022-10-04 9:21 ` Conor Dooley 2022-10-04 9:21 ` Conor Dooley 2022-10-04 9:24 ` Conor Dooley 2022-10-04 9:24 ` Conor Dooley 2022-10-06 9:07 ` Geert Uytterhoeven 2022-10-06 9:07 ` Geert Uytterhoeven 2022-09-30 7:33 ` [PATCH v1 24/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Hal Feng 2022-09-30 7:33 ` Hal Feng 2022-09-30 11:00 ` Krzysztof Kozlowski 2022-09-30 11:00 ` Krzysztof Kozlowski 2022-09-30 7:38 ` [PATCH v1 25/30] dt-bindings: pinctrl: Add StarFive JH7110 pinctrl bindings Hal Feng 2022-09-30 7:38 ` Hal Feng 2022-09-30 11:05 ` Krzysztof Kozlowski 2022-09-30 11:05 ` Krzysztof Kozlowski 2022-09-30 12:16 ` Rob Herring 2022-09-30 12:16 ` Rob Herring 2022-10-20 7:28 ` Icenowy Zheng 2022-10-20 7:28 ` Icenowy Zheng 2022-09-30 7:43 ` [PATCH v1 26/30] pinctrl: starfive: Add StarFive JH7110 driver Hal Feng 2022-09-30 7:43 ` Hal Feng 2022-10-01 14:35 ` kernel test robot 2022-10-01 14:35 ` kernel test robot 2022-10-04 8:56 ` Linus Walleij 2022-10-04 8:56 ` Linus Walleij 2022-10-05 13:31 ` Emil Renner Berthing 2022-10-05 13:31 ` Emil Renner Berthing 2022-10-14 2:05 ` Hal Feng 2022-10-14 2:05 ` Hal Feng 2022-09-30 7:49 ` [PATCH v1 27/30] RISC-V: Add initial StarFive JH7110 device tree Hal Feng 2022-09-30 7:49 ` Hal Feng 2022-10-01 10:52 ` Conor Dooley 2022-10-01 10:52 ` Conor Dooley 2022-10-03 7:45 ` Krzysztof Kozlowski 2022-10-03 7:45 ` Krzysztof Kozlowski 2022-10-14 9:41 ` Hal Feng 2022-10-14 9:41 ` Hal Feng 2022-09-30 7:53 ` [PATCH v1 28/30] RISC-V: Add StarFive JH7110 VisionFive2 board " Hal Feng 2022-09-30 7:53 ` Hal Feng 2022-10-01 11:14 ` Conor Dooley 2022-10-01 11:14 ` Conor Dooley 2022-10-29 8:18 ` Hal Feng 2022-10-29 8:18 ` Hal Feng 2022-09-30 9:06 ` [PATCH v1 29/30] RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW Hal Feng 2022-09-30 9:06 ` Hal Feng 2022-09-30 20:54 ` Ben Dooks 2022-09-30 20:54 ` Ben Dooks 2022-09-30 21:41 ` Conor Dooley 2022-09-30 21:41 ` Conor Dooley 2022-10-14 3:24 ` Hal Feng 2022-10-14 3:24 ` Hal Feng 2022-09-30 12:23 ` [PATCH v1 30/30] RISC-V: Add StarFive JH7100 and JH7110 SoC Kconfig options Hal Feng 2022-09-30 12:23 ` Hal Feng 2022-09-30 12:37 ` Conor Dooley 2022-09-30 12:37 ` Conor Dooley 2022-10-11 18:32 ` Hal Feng 2022-10-11 18:32 ` Hal Feng 2022-10-05 13:05 ` [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Emil Renner Berthing 2022-10-05 13:05 ` Emil Renner Berthing 2022-10-08 3:18 ` Hal Feng 2022-10-08 3:18 ` Hal Feng
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