From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <robert.foss@linaro.org>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Subject: [PATCH v2 4/7] arm64: dts: renesas: r8a779g0: Add display related nodes Date: Wed, 23 Nov 2022 08:59:43 +0200 [thread overview] Message-ID: <20221123065946.40415-5-tomi.valkeinen+renesas@ideasonboard.com> (raw) In-Reply-To: <20221123065946.40415-1-tomi.valkeinen+renesas@ideasonboard.com> Add DT nodes for components needed to get the DSI output working: - FCPv - VSPd - DU - DSI Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 130 ++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 45d8d927ad26..4577208963b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1203,6 +1203,136 @@ gic: interrupt-controller@f1000000 { (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x7000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x7000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Neil Armstrong <neil.armstrong@linaro.org>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Robert Foss <robert.foss@linaro.org>, Andrzej Hajda <andrzej.hajda@intel.com>, Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Subject: [PATCH v2 4/7] arm64: dts: renesas: r8a779g0: Add display related nodes Date: Wed, 23 Nov 2022 08:59:43 +0200 [thread overview] Message-ID: <20221123065946.40415-5-tomi.valkeinen+renesas@ideasonboard.com> (raw) In-Reply-To: <20221123065946.40415-1-tomi.valkeinen+renesas@ideasonboard.com> Add DT nodes for components needed to get the DSI output working: - FCPv - VSPd - DU - DSI Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 130 ++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 45d8d927ad26..4577208963b3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1203,6 +1203,136 @@ gic: interrupt-controller@f1000000 { (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x7000>; + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 830>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x7000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 831>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 831>; + + renesas,fcp = <&fcpvd1>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779g0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>, <&vspd1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779g0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 416>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- 2.34.1
next prev parent reply other threads:[~2022-11-23 7:00 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-23 6:59 [PATCH v2 0/7] Renesas V4H DSI & DP output support Tomi Valkeinen 2022-11-23 6:59 ` Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 1/7] dt-bindings: display: renesas,du: Provide bindings for r8a779g0 Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 1/7] dt-bindings: display: renesas, du: " Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 2/7] dt-bindings: display: bridge: renesas,dsi-csi2-tx: Add r8a779g0 Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 2/7] dt-bindings: display: bridge: renesas, dsi-csi2-tx: " Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 3/7] clk: renesas: r8a779g0: Add display related clocks Tomi Valkeinen 2022-11-23 6:59 ` Tomi Valkeinen 2022-11-30 19:18 ` Geert Uytterhoeven 2022-11-30 19:18 ` Geert Uytterhoeven 2022-12-01 9:06 ` Tomi Valkeinen 2022-12-01 9:06 ` Tomi Valkeinen 2022-12-01 9:34 ` Geert Uytterhoeven 2022-12-01 9:34 ` Geert Uytterhoeven 2022-12-01 9:26 ` Tomi Valkeinen 2022-12-01 9:26 ` Tomi Valkeinen 2022-12-01 9:45 ` Geert Uytterhoeven 2022-12-01 9:45 ` Geert Uytterhoeven 2022-11-23 6:59 ` Tomi Valkeinen [this message] 2022-11-23 6:59 ` [PATCH v2 4/7] arm64: dts: renesas: r8a779g0: Add display related nodes Tomi Valkeinen 2022-12-01 9:20 ` Geert Uytterhoeven 2022-12-01 9:20 ` Geert Uytterhoeven 2022-11-23 6:59 ` [PATCH v2 5/7] arm64: dts: renesas: white-hawk-cpu: Add DP output support Tomi Valkeinen 2022-11-23 6:59 ` Tomi Valkeinen 2022-12-01 10:03 ` Geert Uytterhoeven 2022-12-01 10:03 ` Geert Uytterhoeven 2022-11-23 6:59 ` [PATCH v2 6/7] drm: rcar-du: Add r8a779g0 support Tomi Valkeinen 2022-11-23 6:59 ` Tomi Valkeinen 2022-11-23 6:59 ` [PATCH v2 7/7] drm: rcar-du: dsi: " Tomi Valkeinen 2022-11-23 6:59 ` Tomi Valkeinen 2022-11-29 1:49 ` Laurent Pinchart 2022-11-29 1:49 ` Laurent Pinchart 2022-11-29 11:30 ` Tomi Valkeinen 2022-11-29 11:30 ` Tomi Valkeinen 2022-11-29 11:40 ` Biju Das 2022-11-29 11:40 ` Biju Das 2022-11-29 11:49 ` Geert Uytterhoeven 2022-11-29 11:49 ` Geert Uytterhoeven 2022-11-29 12:05 ` Laurent Pinchart 2022-11-29 12:05 ` Laurent Pinchart 2022-11-29 12:59 ` Tomi Valkeinen 2022-11-29 12:59 ` Tomi Valkeinen 2022-11-29 13:41 ` [PATCH v3 7/7] drm: rcar-du: dsi: Add r8A779g0 support Tomi Valkeinen 2022-11-29 13:41 ` Tomi Valkeinen 2022-11-29 17:44 ` Laurent Pinchart 2022-11-29 17:44 ` Laurent Pinchart 2022-11-30 8:08 ` [PATCH v4 " Tomi Valkeinen 2022-11-30 8:08 ` Tomi Valkeinen 2022-11-29 1:58 ` [PATCH v2 0/7] Renesas V4H DSI & DP output support Laurent Pinchart 2022-11-29 1:58 ` Laurent Pinchart
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