From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, <ajones@ventanamicro.com>, <aou@eecs.berkeley.edu>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <guoren@kernel.org>, <heiko@sntech.de>, <krzysztof.kozlowski+dt@linaro.org>, <linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <robh+dt@kernel.org> Subject: [RFC 0/2] Putting some basic order on isa extension stuff Date: Tue, 29 Nov 2022 14:47:41 +0000 [thread overview] Message-ID: <20221129144742.2935581-1-conor.dooley@microchip.com> (raw) In-Reply-To: <Y4XvnHIPw8ZuBZEk@wendy> RFC: - I have not even tested this, I just did an allmodconfig - I don't know if I re-ordered something that is sacrosanct - I don't know if I changed all of the instances - I didn't write a proper commit message for "patch" 2/2 With those caveats out of the way - all I did here was try to make things consistent so that it'd be easier to point patch submitters at a "do this order please". I never know which of these can be moved without breaking stuff - but they all seem to be internal use stuff since they're not in uapi? @drew, I didn't touch the KVM ones - are they re-sortable too? My base here is rc7 so if you did a reorder at any point there I'd not see it ;) CC: conor.dooley@microchip.com CC: ajones@ventanamicro.com CC: aou@eecs.berkeley.edu CC: conor@kernel.org CC: devicetree@vger.kernel.org CC: guoren@kernel.org CC: heiko@sntech.de CC: krzysztof.kozlowski+dt@linaro.org CC: linux-kernel@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: palmer@dabbelt.com CC: paul.walmsley@sifive.com CC: robh+dt@kernel.org Conor Dooley (2): RISC-V: clarify ISA string ordering rules in cpu.c RISC-V: resort all extensions in "canonical" order arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 26 +++++++++++++++++++------- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 24 insertions(+), 12 deletions(-) -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, <ajones@ventanamicro.com>, <aou@eecs.berkeley.edu>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <guoren@kernel.org>, <heiko@sntech.de>, <krzysztof.kozlowski+dt@linaro.org>, <linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <robh+dt@kernel.org> Subject: [RFC 0/2] Putting some basic order on isa extension stuff Date: Tue, 29 Nov 2022 14:47:41 +0000 [thread overview] Message-ID: <20221129144742.2935581-1-conor.dooley@microchip.com> (raw) In-Reply-To: <Y4XvnHIPw8ZuBZEk@wendy> RFC: - I have not even tested this, I just did an allmodconfig - I don't know if I re-ordered something that is sacrosanct - I don't know if I changed all of the instances - I didn't write a proper commit message for "patch" 2/2 With those caveats out of the way - all I did here was try to make things consistent so that it'd be easier to point patch submitters at a "do this order please". I never know which of these can be moved without breaking stuff - but they all seem to be internal use stuff since they're not in uapi? @drew, I didn't touch the KVM ones - are they re-sortable too? My base here is rc7 so if you did a reorder at any point there I'd not see it ;) CC: conor.dooley@microchip.com CC: ajones@ventanamicro.com CC: aou@eecs.berkeley.edu CC: conor@kernel.org CC: devicetree@vger.kernel.org CC: guoren@kernel.org CC: heiko@sntech.de CC: krzysztof.kozlowski+dt@linaro.org CC: linux-kernel@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: palmer@dabbelt.com CC: paul.walmsley@sifive.com CC: robh+dt@kernel.org Conor Dooley (2): RISC-V: clarify ISA string ordering rules in cpu.c RISC-V: resort all extensions in "canonical" order arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 26 +++++++++++++++++++------- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 24 insertions(+), 12 deletions(-) -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-29 14:51 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-24 13:04 [PATCH 0/2] riscv,isa fixups Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-24 13:04 ` [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-25 1:12 ` Guo Ren 2022-11-25 1:12 ` Guo Ren 2022-11-24 13:04 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:52 ` Conor Dooley 2022-11-24 13:52 ` Conor Dooley 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 19:17 ` Conor Dooley 2022-11-28 19:17 ` Conor Dooley 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-29 5:19 ` Andrew Jones 2022-11-29 5:19 ` Andrew Jones 2022-11-29 11:40 ` Conor Dooley 2022-11-29 11:40 ` Conor Dooley 2022-11-29 14:47 ` Conor Dooley [this message] 2022-11-29 14:47 ` [RFC 0/2] Putting some basic order on isa extension stuff Conor Dooley 2022-11-29 15:48 ` Andrew Jones 2022-11-29 15:48 ` Andrew Jones 2022-11-29 16:50 ` Conor Dooley 2022-11-29 16:50 ` Conor Dooley 2022-11-29 14:47 ` [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:54 ` Conor Dooley 2022-11-29 16:54 ` Conor Dooley 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:48 ` Conor Dooley 2022-11-29 17:48 ` Conor Dooley 2022-11-29 14:47 ` [RFC 2/2] RISC-V: resort all extensions in "canonical" order Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 16:35 ` Andrew Jones 2022-11-29 16:35 ` Andrew Jones 2022-12-01 13:51 ` [PATCH] Documentation: riscv: note that counter access is part of the uABI Conor Dooley 2022-12-01 13:51 ` Conor Dooley 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:56 ` Conor Dooley 2022-12-03 10:56 ` Conor Dooley 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:46 ` Conor Dooley 2023-01-09 21:46 ` Conor Dooley 2022-11-25 1:13 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Guo Ren 2022-11-25 1:13 ` Guo Ren
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