From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, <ajones@ventanamicro.com>, <aou@eecs.berkeley.edu>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <guoren@kernel.org>, <heiko@sntech.de>, <krzysztof.kozlowski+dt@linaro.org>, <linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <robh+dt@kernel.org> Subject: [RFC 2/2] RISC-V: resort all extensions in "canonical" order Date: Tue, 29 Nov 2022 14:47:43 +0000 [thread overview] Message-ID: <20221129144742.2935581-3-conor.dooley@microchip.com> (raw) In-Reply-To: <Y4XvnHIPw8ZuBZEk@wendy> Per the comment in cpu.c, re-sort all lists/tables/enums/whatever in arch/riscv (apart from KVM) in the current edition of what the isa manual considers to be "canonical" order. None of this is in uapi, so we are free to re-order it? I'm never sure when it comes to hwcap... Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..d7d5f27619ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,12 +53,12 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZICBOM = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5e42c92a8456..1d0fa0ebf6a8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -150,12 +150,12 @@ device_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..d3df72c4b94f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,12 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); } #undef SET_ISA_EXT_MAP } -- 2.38.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> Cc: Conor Dooley <conor.dooley@microchip.com>, <ajones@ventanamicro.com>, <aou@eecs.berkeley.edu>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <guoren@kernel.org>, <heiko@sntech.de>, <krzysztof.kozlowski+dt@linaro.org>, <linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <robh+dt@kernel.org> Subject: [RFC 2/2] RISC-V: resort all extensions in "canonical" order Date: Tue, 29 Nov 2022 14:47:43 +0000 [thread overview] Message-ID: <20221129144742.2935581-3-conor.dooley@microchip.com> (raw) In-Reply-To: <Y4XvnHIPw8ZuBZEk@wendy> Per the comment in cpu.c, re-sort all lists/tables/enums/whatever in arch/riscv (apart from KVM) in the current edition of what the isa manual considers to be "canonical" order. None of this is in uapi, so we are free to re-order it? I'm never sure when it comes to hwcap... Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..d7d5f27619ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,12 +53,12 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZICBOM = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5e42c92a8456..1d0fa0ebf6a8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -150,12 +150,12 @@ device_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..d3df72c4b94f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,12 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); } #undef SET_ISA_EXT_MAP } -- 2.38.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-29 14:51 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-24 13:04 [PATCH 0/2] riscv,isa fixups Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-24 13:04 ` [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-25 1:12 ` Guo Ren 2022-11-25 1:12 ` Guo Ren 2022-11-24 13:04 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Conor Dooley 2022-11-24 13:04 ` Conor Dooley 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:42 ` Heiko Stübner 2022-11-24 13:52 ` Conor Dooley 2022-11-24 13:52 ` Conor Dooley 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 17:41 ` Palmer Dabbelt 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:08 ` Conor Dooley 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 18:12 ` Palmer Dabbelt 2022-11-28 19:17 ` Conor Dooley 2022-11-28 19:17 ` Conor Dooley 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-28 23:41 ` Palmer Dabbelt 2022-11-29 5:19 ` Andrew Jones 2022-11-29 5:19 ` Andrew Jones 2022-11-29 11:40 ` Conor Dooley 2022-11-29 11:40 ` Conor Dooley 2022-11-29 14:47 ` [RFC 0/2] Putting some basic order on isa extension stuff Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 15:48 ` Andrew Jones 2022-11-29 15:48 ` Andrew Jones 2022-11-29 16:50 ` Conor Dooley 2022-11-29 16:50 ` Conor Dooley 2022-11-29 14:47 ` [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Conor Dooley 2022-11-29 14:47 ` Conor Dooley 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:12 ` Andrew Jones 2022-11-29 16:54 ` Conor Dooley 2022-11-29 16:54 ` Conor Dooley 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:19 ` Andrew Jones 2022-11-29 17:48 ` Conor Dooley 2022-11-29 17:48 ` Conor Dooley 2022-11-29 14:47 ` Conor Dooley [this message] 2022-11-29 14:47 ` [RFC 2/2] RISC-V: resort all extensions in "canonical" order Conor Dooley 2022-11-29 16:35 ` Andrew Jones 2022-11-29 16:35 ` Andrew Jones 2022-12-01 13:51 ` [PATCH] Documentation: riscv: note that counter access is part of the uABI Conor Dooley 2022-12-01 13:51 ` Conor Dooley 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-01 19:21 ` Palmer Dabbelt 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:38 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:45 ` Jonathan Corbet 2022-12-03 10:56 ` Conor Dooley 2022-12-03 10:56 ` Conor Dooley 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:36 ` Atish Patra 2023-01-09 21:46 ` Conor Dooley 2023-01-09 21:46 ` Conor Dooley 2022-11-25 1:13 ` [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order Guo Ren 2022-11-25 1:13 ` Guo Ren
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