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From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Zhenyu Wang <zhenyu.z.wang@intel.com>,
	Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH 09/18] i386: Fix comment style in topology.h
Date: Thu,  2 Feb 2023 17:49:20 +0800	[thread overview]
Message-ID: <20230202094929.343799-10-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20230202094929.343799-1-zhao1.liu@linux.intel.com>

From: Zhao Liu <zhao1.liu@intel.com>

For function comments in this file, keep the comment style consistent
with other places.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 include/hw/i386/topology.h | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index b0174c18b7bd..5de905dc00d3 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -24,7 +24,8 @@
 #ifndef HW_I386_TOPOLOGY_H
 #define HW_I386_TOPOLOGY_H
 
-/* This file implements the APIC-ID-based CPU topology enumeration logic,
+/*
+ * This file implements the APIC-ID-based CPU topology enumeration logic,
  * documented at the following document:
  *   Intel® 64 Architecture Processor Topology Enumeration
  *   http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
@@ -41,7 +42,8 @@
 
 #include "qemu/bitops.h"
 
-/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
+/*
+ * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
  */
 typedef uint32_t apic_id_t;
 
@@ -60,8 +62,7 @@ typedef struct X86CPUTopoInfo {
     unsigned threads_per_core;
 } X86CPUTopoInfo;
 
-/* Return the bit width needed for 'count' IDs
- */
+/* Return the bit width needed for 'count' IDs */
 static unsigned apicid_bitwidth_for_count(unsigned count)
 {
     g_assert(count >= 1);
@@ -69,15 +70,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
     return count ? 32 - clz32(count) : 0;
 }
 
-/* Bit width of the SMT_ID (thread ID) field on the APIC ID
- */
+/* Bit width of the SMT_ID (thread ID) field on the APIC ID */
 static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
 {
     return apicid_bitwidth_for_count(topo_info->threads_per_core);
 }
 
-/* Bit width of the Core_ID field
- */
+/* Bit width of the Core_ID field */
 static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
 {
     /*
@@ -94,8 +93,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
     return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
 }
 
-/* Bit offset of the Core_ID field
- */
+/* Bit offset of the Core_ID field */
 static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
 {
     return apicid_smt_width(topo_info);
@@ -107,14 +105,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
     return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
 }
 
-/* Bit offset of the Pkg_ID (socket ID) field
- */
+/* Bit offset of the Pkg_ID (socket ID) field */
 static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
 {
     return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
 }
 
-/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
+/*
+ * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
  *
  * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
  */
@@ -127,7 +125,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
            topo_ids->smt_id;
 }
 
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
  * based on (contiguous) CPU index
  */
 static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
@@ -154,7 +153,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
     topo_ids->smt_id = cpu_index % nr_threads;
 }
 
-/* Calculate thread/core/package IDs for a specific topology,
+/*
+ * Calculate thread/core/package IDs for a specific topology,
  * based on APIC ID
  */
 static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
@@ -178,7 +178,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
     topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
 }
 
-/* Make APIC ID for the CPU 'cpu_index'
+/*
+ * Make APIC ID for the CPU 'cpu_index'
  *
  * 'cpu_index' is a sequential, contiguous ID for the CPU.
  */
-- 
2.34.1



  parent reply	other threads:[~2023-02-02  9:46 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-02  9:49 [PATCH 00/18] Support smp.clusters for x86 Zhao Liu
2023-02-02  9:49 ` [PATCH 01/18] machine: Fix comment of machine_parse_smp_config() Zhao Liu
2023-02-02  9:49 ` [PATCH 02/18] tests: Rename test-x86-cpuid.c to test-x86-apicid.c Zhao Liu
2023-02-02  9:49 ` [PATCH 03/18] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-02-02  9:49 ` [PATCH 04/18] i386/cpu: Fix number of addressable IDs in CPUID.04H Zhao Liu
2023-02-02  9:49 ` [PATCH 05/18] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-02-02  9:49 ` [PATCH 06/18] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-02-02  9:49 ` [PATCH 07/18] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-02-02  9:49 ` [PATCH 08/18] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-02-02  9:49 ` Zhao Liu [this message]
2023-02-02  9:49 ` [PATCH 10/18] i386: Update APIC ID parsing rule to support module level Zhao Liu
2023-02-02  9:49 ` [PATCH 11/18] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-02-02  9:49 ` [PATCH 12/18] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-02-02  9:49 ` [PATCH 13/18] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-02-02  9:49 ` [PATCH 14/18] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-02-02  9:49 ` [PATCH 15/18] i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14] Zhao Liu
2023-02-02  9:49 ` [PATCH 16/18] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-02-02  9:49 ` [PATCH 17/18] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-02-02  9:49 ` [PATCH 18/18] i386: Add new property to control L2 cache topo in CPUID.04H Zhao Liu

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