From: Evan Green <evan@rivosinc.com> To: Palmer Dabbelt <palmer@rivosinc.com> Cc: Anup Patel <apatel@ventanamicro.com>, Albert Ou <aou@eecs.berkeley.edu>, heiko@sntech.de, Atish Patra <atishp@rivosinc.com>, Randy Dunlap <rdunlap@infradead.org>, vineetg@rivosinc.com, linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>, Conor Dooley <conor.dooley@microchip.com>, Evan Green <evan@rivosinc.com>, Palmer Dabbelt <palmer@dabbelt.com>, slewis@rivosinc.com, Paul Walmsley <paul.walmsley@sifive.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, Dao Lu <daolu@rivosinc.com>, linux-riscv@lists.infradead.org, Andrew Jones <ajones@ventanamicro.com> Subject: [PATCH v4 1/6] RISC-V: Move struct riscv_cpuinfo to new header Date: Tue, 14 Mar 2023 11:32:15 -0700 [thread overview] Message-ID: <20230314183220.513101-2-evan@rivosinc.com> (raw) In-Reply-To: <20230314183220.513101-1-evan@rivosinc.com> In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green <evan@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- (no changes since v3) Changes in v3: - Updated copyright date in cpufeature.h - Fixed typo in cpufeature.h comment (Conor) Changes in v2: - Factored the move of struct riscv_cpuinfo to its own header arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 000000000000..66ebaae449c8 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022-2023 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the corresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/cpufeature.h> #include <asm/csr.h> #include <asm/hwcap.h> #include <asm/sbi.h> @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) { -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Evan Green <evan@rivosinc.com> To: Palmer Dabbelt <palmer@rivosinc.com> Cc: slewis@rivosinc.com, heiko@sntech.de, Conor Dooley <conor@kernel.org>, vineetg@rivosinc.com, Evan Green <evan@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Albert Ou <aou@eecs.berkeley.edu>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com>, Dao Lu <daolu@rivosinc.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Randy Dunlap <rdunlap@infradead.org>, Sunil V L <sunilvl@ventanamicro.com>, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 1/6] RISC-V: Move struct riscv_cpuinfo to new header Date: Tue, 14 Mar 2023 11:32:15 -0700 [thread overview] Message-ID: <20230314183220.513101-2-evan@rivosinc.com> (raw) In-Reply-To: <20230314183220.513101-1-evan@rivosinc.com> In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green <evan@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- (no changes since v3) Changes in v3: - Updated copyright date in cpufeature.h - Fixed typo in cpufeature.h comment (Conor) Changes in v2: - Factored the move of struct riscv_cpuinfo to its own header arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 000000000000..66ebaae449c8 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022-2023 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the corresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include <linux/init.h> #include <linux/seq_file.h> #include <linux/of.h> +#include <asm/cpufeature.h> #include <asm/csr.h> #include <asm/hwcap.h> #include <asm/sbi.h> @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) { -- 2.25.1
next prev parent reply other threads:[~2023-03-14 18:32 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-14 18:32 [PATCH v4 0/6] RISC-V Hardware Probing User Interface Evan Green 2023-03-14 18:32 ` Evan Green [this message] 2023-03-14 18:32 ` [PATCH v4 1/6] RISC-V: Move struct riscv_cpuinfo to new header Evan Green 2023-03-21 20:22 ` Heiko Stübner 2023-03-21 20:22 ` Heiko Stübner 2023-03-14 18:32 ` [PATCH v4 2/6] RISC-V: Add a syscall for HW probing Evan Green 2023-03-14 18:32 ` Evan Green 2023-03-21 20:23 ` Heiko Stübner 2023-03-21 20:23 ` Heiko Stübner 2023-03-14 18:32 ` [PATCH v4 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Evan Green 2023-03-14 18:32 ` Evan Green 2023-03-21 16:41 ` Heiko Stübner 2023-03-21 16:41 ` Heiko Stübner 2023-03-22 16:17 ` Evan Green 2023-03-22 16:17 ` Evan Green 2023-03-21 20:25 ` Heiko Stübner 2023-03-21 20:25 ` Heiko Stübner 2023-03-22 15:35 ` Conor Dooley 2023-03-22 15:35 ` Conor Dooley 2023-03-22 16:04 ` Evan Green 2023-03-22 16:04 ` Evan Green 2023-03-14 18:32 ` [PATCH v4 4/6] RISC-V: hwprobe: Support probing of misaligned access performance Evan Green 2023-03-14 18:32 ` Evan Green 2023-03-17 10:08 ` Heiko Stübner 2023-03-17 10:08 ` Heiko Stübner 2023-03-21 15:35 ` Evan Green 2023-03-21 15:35 ` Evan Green 2023-03-18 12:02 ` Conor Dooley 2023-03-18 12:02 ` Conor Dooley 2023-03-21 20:27 ` Heiko Stübner 2023-03-21 20:27 ` Heiko Stübner 2023-03-14 18:32 ` [PATCH v4 5/6] selftests: Test the new RISC-V hwprobe interface Evan Green 2023-03-14 18:32 ` Evan Green 2023-03-14 18:32 ` [PATCH v4 6/6] RISC-V: Add hwprobe vDSO function and data Evan Green 2023-03-14 18:32 ` Evan Green 2023-03-17 11:08 ` kernel test robot 2023-03-17 11:08 ` kernel test robot 2023-03-17 12:10 ` kernel test robot 2023-03-17 12:10 ` kernel test robot 2023-03-21 20:32 ` [PATCH v4 0/6] RISC-V Hardware Probing User Interface Heiko Stübner
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