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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liweiwei@iscas.ac.cn,
	zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH for-8.1 v3 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
Date: Sat, 18 Mar 2023 17:04:19 -0300	[thread overview]
Message-ID: <20230318200436.299464-10-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230318200436.299464-1-dbarboza@ventanamicro.com>

We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.

The result is that these 4 configs are being set every time, and every
other CPU should always account for them. CPUs such as sifive_e need to
disable settings that aren't enabled simply because the parent class
happens to be enabling it.

Moving all configurations from the parent class to each CPU will
centralize the config of each CPU into its own init(), which is clearer
than having to account to whatever happens to be set in the parent
device. These settings are also being set in register_cpu_props() when
no 'misa_ext' is set, so for these CPUs we don't need changes. Named
CPUs will receive all cfgs that the parent were setting into their
init().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 48 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fef55d7d79..c7b6e7b84b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -325,7 +325,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
 
 static void riscv_any_cpu_init(Object *obj)
 {
-    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
 #if defined(TARGET_RISCV32)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #elif defined(TARGET_RISCV64)
@@ -340,6 +341,12 @@ static void riscv_any_cpu_init(Object *obj)
 
     env->priv_ver = PRIV_VERSION_LATEST;
     register_cpu_props(obj);
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.mmu = true;
+    cpu->cfg.pmp = true;
 }
 
 #if defined(TARGET_RISCV64)
@@ -358,13 +365,20 @@ static void rv64_base_cpu_init(Object *obj)
 
 static void rv64_sifive_u_cpu_init(Object *obj)
 {
-    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     register_cpu_props(obj);
     env->priv_ver = PRIV_VERSION_1_10_0;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.mmu = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv64_sifive_e_cpu_init(Object *obj)
@@ -375,10 +389,14 @@ static void rv64_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     register_cpu_props(obj);
     env->priv_ver = PRIV_VERSION_1_10_0;
-    cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv64_thead_c906_cpu_init(Object *obj)
@@ -411,6 +429,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv128_base_cpu_init(Object *obj)
@@ -447,7 +469,8 @@ static void rv32_base_cpu_init(Object *obj)
 
 static void rv32_sifive_u_cpu_init(Object *obj)
 {
-    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+    CPURISCVState *env = &cpu->env;
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 
     register_cpu_props(obj);
@@ -455,6 +478,12 @@ static void rv32_sifive_u_cpu_init(Object *obj)
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.mmu = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv32_sifive_e_cpu_init(Object *obj)
@@ -465,10 +494,14 @@ static void rv32_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     register_cpu_props(obj);
     env->priv_ver = PRIV_VERSION_1_10_0;
-    cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv32_ibex_cpu_init(Object *obj)
@@ -479,11 +512,15 @@ static void rv32_ibex_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     register_cpu_props(obj);
     env->priv_ver = PRIV_VERSION_1_11_0;
-    cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 #endif
     cpu->cfg.epmp = true;
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.pmp = true;
 }
 
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -494,10 +531,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     register_cpu_props(obj);
     env->priv_ver = PRIV_VERSION_1_10_0;
-    cpu->cfg.mmu = false;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
 #endif
+
+    /* inherited from parent obj via riscv_cpu_init() */
+    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.pmp = true;
 }
 #endif
 
@@ -1384,11 +1425,6 @@ static void riscv_cpu_init(Object *obj)
 {
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    cpu->cfg.ext_ifencei = true;
-    cpu->cfg.ext_icsr = true;
-    cpu->cfg.mmu = true;
-    cpu->cfg.pmp = true;
-
     cpu_set_cpustate_pointers(cpu);
 
 #ifndef CONFIG_USER_ONLY
-- 
2.39.2



  parent reply	other threads:[~2023-03-18 20:05 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-18 20:04 [PATCH for-8.1 v3 00/26] target/riscv: rework CPU extensions validation Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v() Daniel Henrique Barboza
2023-03-21  1:47   ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 02/26] target/riscv/cpu.c: remove set_vext_version() Daniel Henrique Barboza
2023-03-21  1:49   ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 03/26] target/riscv/cpu.c: remove set_priv_version() Daniel Henrique Barboza
2023-03-21  1:50   ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 04/26] target/riscv: add PRIV_VERSION_LATEST Daniel Henrique Barboza
2023-03-21  1:50   ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Daniel Henrique Barboza
2023-03-21  4:51   ` LIU Zhiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init() Daniel Henrique Barboza
2023-03-18 20:04 ` Daniel Henrique Barboza [this message]
2023-03-18 20:04 ` [PATCH for-8.1 v3 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 11/26] target/riscv/cpu.c: set cpu config in set_misa() Daniel Henrique Barboza
2023-03-21  3:54   ` liweiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 12/26] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 14/26] target/riscv: add RVG Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 15/26] target/riscv/cpu.c: split RVG code from validate_set_extensions() Daniel Henrique Barboza
2023-03-21  3:10   ` liweiwei
2023-03-18 20:04 ` [PATCH for-8.1 v3 16/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_ext() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 17/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 18/26] target/riscv: error out on priv failure for RVH Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 19/26] target/riscv: write env->misa_ext* in register_generic_cpu_props() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 20/26] target/riscv: make validate_misa_ext() use a misa_ext val Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 21/26] target/riscv: split riscv_cpu_validate_set_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 22/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 23/26] target/riscv: rework write_misa() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 24/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 25/26] target/riscv: allow write_misa() to enable RVG Daniel Henrique Barboza
2023-03-21  3:25   ` liweiwei
2023-03-22 17:42     ` Daniel Henrique Barboza
2023-03-18 20:04 ` [PATCH for-8.1 v3 26/26] target/riscv: allow write_misa() to enable RVV Daniel Henrique Barboza
2023-03-21  3:41   ` liweiwei
2023-03-22 17:39     ` Daniel Henrique Barboza

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