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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Vincent Chen <vincent.chen@sifive.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Guo Ren <guoren@kernel.org>,
	Alexandre Ghiti <alexandre.ghiti@canonical.com>
Subject: [PATCH -next v17 04/20] riscv: Clear vector regfile on bootup
Date: Mon, 27 Mar 2023 16:49:24 +0000	[thread overview]
Message-ID: <20230327164941.20491-5-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230327164941.20491-1-andy.chiu@sifive.com>

From: Greentime Hu <greentime.hu@sifive.com>

clear vector registers on boot if kernel supports V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..3fd6a4bd9c3e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -392,7 +392,7 @@ ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	beqz	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done_fpu
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@ ENTRY(reset_regs)
 	fmv.s.x	f31, zero
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
+.Lreset_regs_done_fpu:
 #endif /* CONFIG_FPU */
-.Lreset_regs_done:
+
+#ifdef CONFIG_RISCV_ISA_V
+	csrr	t0, CSR_MISA
+	li	t1, COMPAT_HWCAP_ISA_V
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done_vector
+
+	/*
+	 * Clear vector registers and reset vcsr
+	 * VLMAX has a defined value, VLEN is a constant,
+	 * and this form of vsetvli is defined to set vl to VLMAX.
+	 */
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	csrs	CSR_VCSR, x0
+	vsetvli t1, x0, e8, m8, ta, ma
+	vmv.v.i v0, 0
+	vmv.v.i v8, 0
+	vmv.v.i v16, 0
+	vmv.v.i v24, 0
+	/* note that the caller must clear SR_VS */
+.Lreset_regs_done_vector:
+#endif /* CONFIG_RISCV_ISA_V */
 	ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Vincent Chen <vincent.chen@sifive.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Guo Ren <guoren@kernel.org>,
	Alexandre Ghiti <alexandre.ghiti@canonical.com>
Subject: [PATCH -next v17 04/20] riscv: Clear vector regfile on bootup
Date: Mon, 27 Mar 2023 16:49:24 +0000	[thread overview]
Message-ID: <20230327164941.20491-5-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230327164941.20491-1-andy.chiu@sifive.com>

From: Greentime Hu <greentime.hu@sifive.com>

clear vector registers on boot if kernel supports V.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4bf6c449d78b..3fd6a4bd9c3e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -392,7 +392,7 @@ ENTRY(reset_regs)
 #ifdef CONFIG_FPU
 	csrr	t0, CSR_MISA
 	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
-	beqz	t0, .Lreset_regs_done
+	beqz	t0, .Lreset_regs_done_fpu
 
 	li	t1, SR_FS
 	csrs	CSR_STATUS, t1
@@ -430,8 +430,31 @@ ENTRY(reset_regs)
 	fmv.s.x	f31, zero
 	csrw	fcsr, 0
 	/* note that the caller must clear SR_FS */
+.Lreset_regs_done_fpu:
 #endif /* CONFIG_FPU */
-.Lreset_regs_done:
+
+#ifdef CONFIG_RISCV_ISA_V
+	csrr	t0, CSR_MISA
+	li	t1, COMPAT_HWCAP_ISA_V
+	and	t0, t0, t1
+	beqz	t0, .Lreset_regs_done_vector
+
+	/*
+	 * Clear vector registers and reset vcsr
+	 * VLMAX has a defined value, VLEN is a constant,
+	 * and this form of vsetvli is defined to set vl to VLMAX.
+	 */
+	li	t1, SR_VS
+	csrs	CSR_STATUS, t1
+	csrs	CSR_VCSR, x0
+	vsetvli t1, x0, e8, m8, ta, ma
+	vmv.v.i v0, 0
+	vmv.v.i v8, 0
+	vmv.v.i v16, 0
+	vmv.v.i v24, 0
+	/* note that the caller must clear SR_VS */
+.Lreset_regs_done_vector:
+#endif /* CONFIG_RISCV_ISA_V */
 	ret
 END(reset_regs)
 #endif /* CONFIG_RISCV_M_MODE */
-- 
2.17.1


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  parent reply	other threads:[~2023-03-27 16:50 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-27 16:49 [PATCH -next v17 00/20] riscv: Add vector ISA support Andy Chiu
2023-03-27 16:49 ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 01/20] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 02/20] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:45   ` Heiko Stübner
2023-03-31 10:45     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 03/20] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 16:03   ` Heiko Stübner
2023-03-31 16:03     ` Heiko Stübner
2023-03-27 16:49 ` Andy Chiu [this message]
2023-03-27 16:49   ` [PATCH -next v17 04/20] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-31 10:53   ` Heiko Stübner
2023-03-31 10:53     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 05/20] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:56   ` Heiko Stübner
2023-03-31 10:56     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 06/20] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 10:56   ` Heiko Stübner
2023-03-31 10:56     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 07/20] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:02   ` Heiko Stübner
2023-03-31 11:02     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 08/20] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:05   ` Heiko Stübner
2023-03-31 11:05     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 09/20] riscv: Add task switch support for vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 11:19   ` Heiko Stübner
2023-03-31 11:19     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 10/20] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-28 17:22   ` Conor Dooley
2023-03-28 17:22     ` Conor Dooley
2023-03-31 14:38     ` Andy Chiu
2023-03-31 14:38       ` Andy Chiu
2023-03-31 13:08   ` Heiko Stübner
2023-03-31 13:08     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 11/20] riscv: Add ptrace vector support Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-28  5:53   ` Rolf Eike Beer
2023-03-28  5:53     ` Rolf Eike Beer
2023-03-28  6:46     ` Andy Chiu
2023-03-28  6:46       ` Andy Chiu
2023-03-27 16:49 ` [PATCH -next v17 12/20] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:21   ` Heiko Stübner
2023-04-01 22:21     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 13/20] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:20   ` Heiko Stübner
2023-04-01 22:20     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 14/20] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-04-01 22:19   ` Heiko Stübner
2023-04-01 22:19     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 15/20] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:43   ` Heiko Stübner
2023-03-31 13:43     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 16/20] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:38   ` Heiko Stübner
2023-03-31 13:38     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 17/20] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:36   ` Heiko Stübner
2023-03-31 13:36     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 18/20] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-27 17:36   ` Anup Patel
2023-03-27 17:36     ` Anup Patel
2023-03-27 16:49 ` [PATCH -next v17 19/20] riscv: detect assembler support for .option arch Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:33   ` Heiko Stübner
2023-03-31 13:33     ` Heiko Stübner
2023-03-27 16:49 ` [PATCH -next v17 20/20] riscv: Enable Vector code to be built Andy Chiu
2023-03-27 16:49   ` Andy Chiu
2023-03-31 13:32   ` Heiko Stübner
2023-03-31 13:32     ` Heiko Stübner

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