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From: fei.yang@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: Fei Yang <fei.yang@intel.com>, dri-devel@lists.freedesktop.org
Subject: [PATCH 3/7] drm/i915/mtl: end support for set caching ioctl
Date: Fri, 31 Mar 2023 23:38:26 -0700	[thread overview]
Message-ID: <20230401063830.438127-4-fei.yang@intel.com> (raw)
In-Reply-To: <20230401063830.438127-1-fei.yang@intel.com>

From: Fei Yang <fei.yang@intel.com>

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache.

Signed-off-by: Fei Yang <fei.yang@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 497de40b8e68..33b73bea1e08 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -335,6 +335,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 	if (IS_DGFX(i915))
 		return -ENODEV;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		return -EOPNOTSUPP;
+
 	switch (args->caching) {
 	case I915_CACHING_NONE:
 		level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..e602c323896b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem,
 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(i915))
+	/*
+	 * MTL doesn't snooping CPU cache by default for GPU access (namely
+	 * 1-way coherency). However some UMD's are currently depending on
+	 * that. Make 1-way coherent the default setting for MTL. A follow
+	 * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+	 * caching mode at BO creation time
+	 */
+	if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: fei.yang@intel.com
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/7] drm/i915/mtl: end support for set caching ioctl
Date: Fri, 31 Mar 2023 23:38:26 -0700	[thread overview]
Message-ID: <20230401063830.438127-4-fei.yang@intel.com> (raw)
In-Reply-To: <20230401063830.438127-1-fei.yang@intel.com>

From: Fei Yang <fei.yang@intel.com>

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache.

Signed-off-by: Fei Yang <fei.yang@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c  | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 497de40b8e68..33b73bea1e08 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -335,6 +335,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 	if (IS_DGFX(i915))
 		return -ENODEV;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		return -EOPNOTSUPP;
+
 	switch (args->caching) {
 	case I915_CACHING_NONE:
 		level = I915_CACHE_NONE;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca6..e602c323896b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem,
 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(i915))
+	/*
+	 * MTL doesn't snooping CPU cache by default for GPU access (namely
+	 * 1-way coherency). However some UMD's are currently depending on
+	 * that. Make 1-way coherent the default setting for MTL. A follow
+	 * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+	 * caching mode at BO creation time
+	 */
+	if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
 		/* On some devices, we can have the GPU use the LLC (the CPU
 		 * cache) for about a 10% performance improvement
 		 * compared to uncached.  Graphics requests other than
-- 
2.25.1


  parent reply	other threads:[~2023-04-01  6:37 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-01  6:38 [PATCH 0/7] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-01  6:38 ` [Intel-gfx] " fei.yang
2023-04-01  6:38 ` [PATCH 1/7] " fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-03 12:50   ` Jani Nikula
2023-04-03 12:50     ` [Intel-gfx] " Jani Nikula
2023-04-06  8:16     ` Andi Shyti
2023-04-06  8:16       ` Andi Shyti
2023-04-06 18:22       ` Yang, Fei
2023-04-06 18:22         ` Yang, Fei
2023-04-06  8:28   ` Das, Nirmoy
2023-04-06 14:55     ` Yang, Fei
2023-04-06 18:13       ` Das, Nirmoy
2023-04-01  6:38 ` [PATCH 2/7] drm/i915/mtl: workaround coherency issue for Media fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-01  6:38 ` fei.yang [this message]
2023-04-01  6:38   ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-04-01  6:38 ` [PATCH 4/7] drm/i915: preparation for using PAT index fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-01  6:38 ` [PATCH 5/7] drm/i915: use pat_index instead of cache_level fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-01  8:30   ` kernel test robot
2023-04-03 14:50   ` Ville Syrjälä
2023-04-03 14:50     ` [Intel-gfx] " Ville Syrjälä
2023-04-03 16:57     ` Yang, Fei
2023-04-03 16:57       ` [Intel-gfx] " Yang, Fei
2023-04-03 17:14       ` Ville Syrjälä
2023-04-03 17:14         ` [Intel-gfx] " Ville Syrjälä
2023-04-03 19:39         ` Yang, Fei
2023-04-03 19:39           ` [Intel-gfx] " Yang, Fei
2023-04-03 19:52           ` Ville Syrjälä
2023-04-03 19:52             ` [Intel-gfx] " Ville Syrjälä
2023-04-06  6:28             ` Yang, Fei
2023-04-06  6:28               ` [Intel-gfx] " Yang, Fei
2023-04-01  6:38 ` [PATCH 6/7] drm/i915: make sure correct pte encode is used fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-01  6:38 ` [PATCH 7/7] drm/i915: Allow user to set cache at BO creation fei.yang
2023-04-01  6:38   ` [Intel-gfx] " fei.yang
2023-04-03 16:02   ` Ville Syrjälä
2023-04-03 16:02     ` [Intel-gfx] " Ville Syrjälä
2023-04-03 16:35     ` Matt Roper
2023-04-03 16:35       ` [Intel-gfx] " Matt Roper
2023-04-03 16:48       ` Ville Syrjälä
2023-04-03 16:48         ` [Intel-gfx] " Ville Syrjälä
2023-04-04 22:15         ` Kenneth Graunke
2023-04-04  7:29   ` Lionel Landwerlin
2023-04-04 16:04     ` Yang, Fei
2023-04-04 16:04       ` Yang, Fei
2023-04-05  7:45       ` Lionel Landwerlin
2023-04-05 20:26         ` Jordan Justen
2023-04-10  8:23           ` Jordan Justen
2023-04-13 20:49             ` Yang, Fei
2023-04-13 20:49               ` Yang, Fei
2023-04-05 23:06         ` Yang, Fei
2023-04-05 23:06           ` Yang, Fei
2023-04-06  9:11   ` Matthew Auld
2023-04-06  9:11     ` [Intel-gfx] " Matthew Auld
2023-04-01  7:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL Patchwork
2023-04-01  7:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-01  7:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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