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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-crypto@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Weili Qian <qianweili@huawei.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Tom Rix <trix@redhat.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Marc Zyngier <maz@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Mark Gross <markgross@kernel.org>,
	Hans de Goede <hdegoede@redhat.com>,
	Zhou Wang <wangzhou1@hisilicon.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	Thomas Gleixner <tglx@linutronix.de>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	"David S . Miller" <davem@davemloft.net>,
	Nathan Chancellor <nathan@kernel.org>,
	Len Brown <lenb@kernel.org>
Subject: [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
Date: Mon, 15 May 2023 11:19:10 +0530	[thread overview]
Message-ID: <20230515054928.2079268-4-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com>

With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in
allmodconfig build. However, build fails with clang and below
error is seen.

drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm
                       "+Q" (*((char __iomem *)fun_base))
                       ^
This is expected error with clang due to the way it is designed.

To fix this issue, move arm64 assembly code under #if.

Link: https://github.com/ClangBuiltLinux/linux/issues/999
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
[sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if]
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/crypto/hisilicon/qm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index ad0c042b5e66..edc6fd44e7ca 100644
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -610,7 +610,10 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
 static void qm_mb_write(struct hisi_qm *qm, const void *src)
 {
 	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
+
+#if IS_ENABLED(CONFIG_ARM64)
 	unsigned long tmp0 = 0, tmp1 = 0;
+#endif
 
 	if (!IS_ENABLED(CONFIG_ARM64)) {
 		memcpy_toio(fun_base, src, 16);
@@ -618,6 +621,7 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
 		return;
 	}
 
+#if IS_ENABLED(CONFIG_ARM64)
 	asm volatile("ldp %0, %1, %3\n"
 		     "stp %0, %1, %2\n"
 		     "dmb oshst\n"
@@ -626,6 +630,7 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
 		       "+Q" (*((char __iomem *)fun_base))
 		     : "Q" (*((char *)src))
 		     : "memory");
+#endif
 }
 
 static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-crypto@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Sunil V L <sunilvl@ventanamicro.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Weili Qian <qianweili@huawei.com>,
	Zhou Wang <wangzhou1@hisilicon.com>,
	Herbert Xu <herbert@gondor.apana.org.au>,
	"David S . Miller" <davem@davemloft.net>,
	Marc Zyngier <maz@kernel.org>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	Hans de Goede <hdegoede@redhat.com>,
	Mark Gross <markgross@kernel.org>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Tom Rix <trix@redhat.com>
Subject: [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
Date: Mon, 15 May 2023 11:19:10 +0530	[thread overview]
Message-ID: <20230515054928.2079268-4-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230515054928.2079268-1-sunilvl@ventanamicro.com>

With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in
allmodconfig build. However, build fails with clang and below
error is seen.

drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm
                       "+Q" (*((char __iomem *)fun_base))
                       ^
This is expected error with clang due to the way it is designed.

To fix this issue, move arm64 assembly code under #if.

Link: https://github.com/ClangBuiltLinux/linux/issues/999
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
[sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if]
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/crypto/hisilicon/qm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index ad0c042b5e66..edc6fd44e7ca 100644
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -610,7 +610,10 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
 static void qm_mb_write(struct hisi_qm *qm, const void *src)
 {
 	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
+
+#if IS_ENABLED(CONFIG_ARM64)
 	unsigned long tmp0 = 0, tmp1 = 0;
+#endif
 
 	if (!IS_ENABLED(CONFIG_ARM64)) {
 		memcpy_toio(fun_base, src, 16);
@@ -618,6 +621,7 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
 		return;
 	}
 
+#if IS_ENABLED(CONFIG_ARM64)
 	asm volatile("ldp %0, %1, %3\n"
 		     "stp %0, %1, %2\n"
 		     "dmb oshst\n"
@@ -626,6 +630,7 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
 		       "+Q" (*((char __iomem *)fun_base))
 		     : "Q" (*((char *)src))
 		     : "memory");
+#endif
 }
 
 static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
-- 
2.34.1


  parent reply	other threads:[~2023-05-15  5:50 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-15  5:49 [PATCH V6 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-15  5:49 ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` Sunil V L [this message]
2023-05-15  5:49   ` [PATCH V6 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Sunil V L
2023-05-15  5:54   ` Herbert Xu
2023-05-15  5:54     ` Herbert Xu
2023-05-15  5:49 ` [PATCH V6 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 08/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 09/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-23 12:01   ` Andrew Jones
2023-05-23 12:01     ` Andrew Jones
2023-05-15  5:49 ` [PATCH V6 10/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 11/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 12/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 13/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 14/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 15/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 16/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 17/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 18/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 19/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-05-15  5:49 ` [PATCH V6 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-05-15  5:49   ` Sunil V L
2023-06-02 14:57 ` (subset) [PATCH V6 00/21] Add basic ACPI support for RISC-V Palmer Dabbelt
2023-06-02 14:57   ` Palmer Dabbelt
2023-06-02 15:11   ` Palmer Dabbelt
2023-06-02 15:11     ` Palmer Dabbelt
2023-06-02 15:50     ` Conor Dooley
2023-06-02 15:50       ` Conor Dooley
2023-06-02 15:54       ` Conor Dooley
2023-06-02 15:54         ` Conor Dooley
2023-06-02 15:00 ` patchwork-bot+linux-riscv
2023-06-02 15:00   ` patchwork-bot+linux-riscv

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